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CS9211 Datasheet(PDF) 19 Page - National Semiconductor (TI) |
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CS9211 Datasheet(HTML) 19 Page - National Semiconductor (TI) |
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19 / 62 page  Revision 2.1 19 www.national.com Functional Description (Continued) 3.2.2 Mode Selection The CS9211 can be configured for various modes depend- ing on the type of LCD panel being connected. The panel type and mode selection is through Offset 404h[21:16] as shown in Table 3-2 on page 20 and described below. • DSTN or TFT and Color or Monochrome: — DSTN or TFT: Allows a common connector to be used for TFT LCD panels and DSTN LCD panels. The system software can configure the CS9211 to operate in a pass-through mode that presents the digital pixel (RGB) input data on the UD/LD output pins to drive a TFT panel on the common connector. The input data is latched internally before being presented at the output pins to better control the timing of the panel interface signals. — Color or Monochrome: Monochrome must be selected for 8-bit DSTN Mode. • 8-Bit DSTN Mode (Monochrome Only): — Supports DSTN panels with 640x480 pixel resolution. — Register programming: Offset 404h[21:16] = 00_1_000. • 8-Bit single scan Color STN Mode: — Supports single scan STN panels with 640x480 color pixel resolution. — Register programming: Offset 404h[21:16] = 00_0_011. • 16-Bit Color DSTN Mode: — Supports DSTN panels with 640x480 or 800x600 color pixel resolutions. — Register programming: Offset 404h[21:16] = 00_0_001. • 24-Bit Color DSTN Mode: — Supports DSTN panels with 1024x768 color pixel resolution. — Register programming: Offset 404h[21:16] = 00_0_010. • TFT One Pixel per Clock Mode: — Supports all TFT panels with up to 18-bit interface. — Register programming: Offset 404h[21:16] = 01_0_000. • TFT Two Pixel per Clock Mode: — Supports 18-bit/24-bit 2pixel/CLK TFT panels. — Register programming: Offset 404h[21:16] = 01_0_001. 3.2.2.1 TFT Mode To enable TFT mode, set Offset 404h[21:20] = 01 (see Table 3-2 on page 20). When TFT mode has been selected, the output from the dither block is fed directly onto the panel data pins UD[11:0] and LD[11:0], in accor- dance with Table 3-4 on page 21, and in sync with the TFT timing signals HSYNC, VSYNC, and LDE. These three tim- ing signals are enabled when Offset 404h[26:24] = 111 (see Table 3-3 on page 20). The TFT panel type must be selected according to Table 3-2. The shift clock output (SHFCLK) varies for each panel type (refer to Table 3-7 on page 24). The pixel data format on the LD/UD pins varies based on the type of TFT panel selected as indicated in Table 3-4. Certain timing selections must be made accord- ing to Table 3-8 "Panel Output Timing Selection Bits" on page 24 (see the discussion in Section 3.2.3 "Timing Sig- nals" on page 22). 3.2.2.2 STN Mode This mode is for either SSTN or DSTN panels. To enable STN mode, set Offset 404h[21:20] = 00 (see Table 3-2). When STN mode has been selected, the output from the dither block is sent through the FRM and the memory con- troller (memory controller: DSTN only), and continues to the panel data pins. The CS9211 will shift out the data on the positive edge of the shift clock (SHFCLK). The shift clock output (SHFCLK) varies for each panel type as showninTable 3-7onpage 24. Thepixel data format on the LD/UD pins varies based on the type of STN panel selected, as indicated in Table 3-4. Certain timing selec- tions must be made according to Table 3-8 "Panel Output Timing Selection Bits" on page 24 (see the discussion in Section 3.2.3 "Timing Signals" on page 22). 3.2.2.3 Output Data Mapping The output of the CS9211 is a 24-bit data bus that is artifi- cially split into two 12-bit data buses by the CS9211’s adopted nomenclature (UD/LD). The output data presented on these buses “moves” from pin to pin depending on the type of panel being used, as determined by the contents of Offset 404h[21:16] (see Table 3-2). The mapping is shown in Table 3-4 on page 21. These out- put buses should be thought of as one 24-bit bus (perhaps named OUT[23:0]) for ease of the designer’s understand- ing and to avoid confusion with panels that have a UD/LD- type data bus nomenclature. |
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