CS9211 datasheet(43/62 Pages) NSC

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PIX_OUT

Pixel Output Format: These bits define the pixel output format. The selection of the pixel output for-

mat in conjunction with the panel type selection (bits [21:20]) and the color/monochrome selection

(bits [19]) determines how the pixel data is formatted before being sent on to the LD/UD pins. These

settings also determine the SHFCLK period for the specific panel.

000 = 8-bit DSTN panel or up to 24-bit TFT panel with one pixel per clock.

Option 1: Mono 8-bit DSTN (bits [21:20] = 00 and bit 19 = 1)

(Color 8-bit DSTN is not supported)

SHFCLK = 1/4 of DOTCLK

Option 2: Color TFT with 1 pixel/clock (bits [21:20] = 01 and bit 19 = 0)

SHFCLK = DOTCLK

001 = 16-bit DSTN panel or 18/24-bit TFT XGA panel with two pixels per clock.

Option 1: Color 16-bit DSTN (bits [21:20] = 00 and bit 19 = 0)

SHFCLK = 1/(3:2:3) of DOTCLK

Option 2: Mono 16-bit DSTN (bits [21:20] = 00 and bit 19 = 1)

SHFCLK = 1/8 of DOTCLK

Option 3: Color 18/24 bit TFT (bits [21:20] = 01 and bit 19 = 0)

SHFCLK = 1/2 of DOTCLK

010 = 24-bit DSTN panel

Color 24-bit DSTN (bits [21:20] = 00 and bit 19 = 0)

(Mono 24-bit DSTN is not supported)

SHFCLK = 1/4 of DOTCLK

011 = 8-bit SSTN panel

Color 8-bit SSTN (bits [21:20] = 00 and bit 19 = 0)

SHFCLK = 1/(3:2:3) of DOTCLK

100, 101, 110, and 111 = Reserved

15:14

RSVD

Reserved: This bit is not defined.

CONT_LPS

Continuous Line Pulses: This bit selects whether line pulses are continuously output or are output

only during the active display time. In most cases, DSTN panels require continuous line pulses (LPs).

This bit will have no effect if the CS9211 is set to TFT mode.

0 = Continuous line pulses.

1 = Line pulses during the display time only.

12:0

RSVD

Reserved: These bits are not defined.

Offset 408h-40Bh

Power Management Register (R/W)

Reset Value = 00000000h

31:28

RSVD

Reserved: These bits are not defined.

PWR_SEQ_SEL

Power Sequence Select: Selects whether to use internal or external power sequence. The power

sequence controls the order in which FP_VDDEN, FP_VCONEN, the data and control signals, and

DISPOFF# become active during power-up, and inactive during power-down.

0 = Use internal power sequencing (phase timing is controlled by bits [24:18].

1 = Use external power sequencing (phase timing is controlled by signals generated from CS5530/

CS550A).

RSVD_0

Reserved.: This bit should always be set to zero.

DISPOFF_CNTL

Display Off Control Source: Selects how DISPOFF# is controlled. Independent control may be used

to disable the backlight to save power, even if the panel is otherwise on.

0 = DISPOFF# is controlled by with the power-up/down sequence, internal or external mode.

1 = DISPOFF# immediately turns the backlight off.

PWR_CNTL

Panel Power Control: Initiates the internal power-up or power-down sequence. When the bit is set

from high-to-low, the internal power-down sequence is initiated with the timings as selected by Offset

408h[20:18]. When the bit is set from low-to-high, the internal power-up sequence is initiated with the

timings as selected by Offset 408h[23:21]. This bit may be read to determine the power status (i.e., on

or off) of the panel. This bit functions as described only if the internal power sequence has been

selected by bit [27]. 0 = Powered down; 1 = Powered up.

PWRUP_PHASE_

Panel Power-Up Phase 2: Selects the interval between enabling FP_VDDEN to enabling panel data

and control signals. 0 = 32 ms ±1.0 ms; 1 = 128 ms ±4.0 ms.

PWRUP_PHASE_

Panel Power-Up Phase 1: Selects the interval between enabling the panel data signals to enabling

FP_VCONEN. 0 = 32 ms ±1.0 ms; 1 = 128 ms ±4.0 ms.

Table 4-2. Configuration Registers (Continued)

Bit

Name

Description

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