Z8FS021 datasheet(41/68 Pages) ZILOG

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PS028806-0315

Standard API Register Set

ZMOTION® Intrusion Detection

Product Specification

Table 13. PIR Status/Control Register 3, 8-Pin SOIC

(ePIR_SC3)

Bit

76543210

Field

Reserved Reserved Reserved Reserved

ANA3

Scan

Request

Reserved

ANA1

Scan

Request*

ANA0

Scan

Request

Control

0000

R/W

Reserved

Dual Pyro

Mode

0R/W

R/W

Address

105H

Note: *ANA1 is reserved for White Light detection when enabled via PIR Status/Control Register 2.

ANAx Scan Request

Analog Channel 0, 1, 3-7 Scan Requested Bits

Set by the application; cleared by the PIR Engine.

These bits allow the user application to request the Engine to perform an A/D conversion on the non-

reserved analog inputs. When requested, the Engine will reconfigure the appropriate I/O pin to a single-

ended, unbuffered input using a 2 Volt reference. It will then take the next sample and store it in the PIR

ADC Result Value Registers and clear all ANAx Scan Request bits. The I/O configuration for the ANAx

pin is not returned to its previous configuration by the Engine. If required, the user application must

perform this task.

If multiple request bits are set simultaneously, the Engine will only scan the lowest-numbered ADC

channel requested and ignore any other requests. The user application should set one request bit, then

poll it to determine when the conversion is complete and the data is ready.

When ADC Scan requests are being serviced by the PIR Engine, ADC conversions on the PIR sensor are

suspended. Therefore, the user application should be careful not to continuously request ADC Scans.

The PIR Process Rate Register in the Advanced API Register Set section can be monitored to ensure the

Engine is receiving enough time to perform its required PIR Sensor ADC scans.

0 = no conversion requested/last conversion completed.

1 = perform a conversion on this channel.

Z8FS021 Datasheet(PDF) 41 Page - Zilog, Inc.

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