STW81200 datasheet(27/58 Pages) STMICROELECTRONICS

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STW81200

Circuit description

It is possible to set the sign of the delay through the PFD_DEL_MODE bit in the ST3

through the PFD_DEL bit in the ST0 Register (2 bit; 0=1.2 ns, 1=1.9 ns, 2=2.5 ns,

3=3.0 ns). Even though the for spur-compensation settings are best optimized case-by-

case, the setup ‘VCO_DIV_delayed + 1.2 ns delay’ is strongly recommended for most

conditions.

Charge pump leakage current

A different way to force an offset value on the PFD+CP characteristics is provided within the

STW81200 by sourcing or sinking a DC leakage current from the charge pump (settings

available in the ST3 Register). The leakage current is 5-bit programmable starting from a

base DC current of 10 µA (it can be doubled to 20 uA by setting bit CP_LEAK_x2 = 1b). The

sign is set by CP_LEAK_DIR bit: 0b = down-leakage (sink), 1b = up-leakage (source).

The resulting delay offset can be calculated as follows:

Experimental results show that down-leakage currents are more effective than up-leakage.

The user must be aware that the use of the leakage current mechanism might impact the

overall phase noise performance by increasing the charge pump noise contribution.

Down-split current

This mechanism is enabled through the DNSPLIT_EN bit (ST3 Register), is the injection of

a down-split current pulse from the charge pump circuit. The current pulse is 16 VCO cycles

wide while the current level is set by the PFD_DEL bit (ST0 Register) among 4 different

possible values: 0, 0.25*ICP, 0.5*ICP or 0.75*ICP.

7.4

Phase frequency detector (PFD)

The PFD takes inputs from the reference and the VCO dividers and produces an output

proportional to the phase error. The PFD includes a delay gate that controls the width of the

anti-backlash pulse (1.2 to 3 ns). This pulse ensures that there is no dead zone in the PFD

transfer function.

Figure 30 shows a simplified schematic of the PFD.

delay

ILEAK

FPFD ICP

⋅

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STW81200 Datasheet(PDF) 27 Page - STMicroelectronics