STW81200 datasheet(45/58 Pages) STMICROELECTRONICS

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DocID025943 Rev 7

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STW81200

Circuit description

ST7 Register

Address:

STW81200BaseAddress + 0x07

Type:

R/W

Description:

Fast Lock control, LD_SDO settings

[26]

RESERVED: must be set to ‘0’

[25]

LD_SDO_tristate: at ‘1’ put LD_SDO out pin in Tri-State mode

[24]

LD_SDO_MODE: LD_SDO output interface mode selection

0: Open Drain mode (Level Range: 1.8V to 3.6V)

1: 2.5V CMOS output mode

[23]

SPI_DATA_OUT_DISABLE: disable auto-switch of LD_SDO pin during SPI read mode

0: LD_SDO pin automatically switched to SPI data out line during SPI read mode

1: LD_SDO pin fixed to Lock detector indication (SPI read operation not possible)

[22:21]

LD_SDO_SEL: LD_SDO Mux output selection bit

00: (0) Lock Detector (default)

01: (1) VCO Divider output (for test purposes only)

10: (2) Calibrator VCO Divider output (for test purposes only)

11: (3) Fast Lock clock output (for test purposes only)

[20]

REGDIG_OCP_DIS: for test purposes only ; must be set to ‘0’ (at ‘1’ disable the over-current protection

of Digital LDO Voltage Regulator)

[19]

CYCLE_SLIP_EN: at ‘1’ enables Cycle Slip feature

[18]

FSTLCK_EN: at ‘1’ enables Fast lock mode using pin #6 (PD_RF2/FL_SW)

[17:13]

CP_SEL_FL: set the Charge Pump current during fast lock time slot (range:0 to 31)

[12:0]

FSTLCK_CNT: Fast-Lock counter value (Range: 2 to 8191); set duration of fast-lock time slot as number

of FPFD cycles

STW81200 Datasheet(PDF) 45 Page - STMicroelectronics