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WM8803CDT/V Datasheet(PDF) 40 Page - Wolfson Microelectronics plc |
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WM8803CDT/V Datasheet(HTML) 40 Page - Wolfson Microelectronics plc |
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40 / 45 page  WM8803 Product Preview w PP Rev 1.1 September 2003 40 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 0 0 0 0 0 0 0 CRC CRC 8 Address Address Address Address Control Control Control Control 16 Track Track Track Track Track Track Track Track 24 Index Index Index Index Index Index Index Index 32 Minute Minute Minute Minute Minute Minute Minute Minute 40 Second Second Second Second Second Second Second Second 48 Frame Frame Frame Frame Frame Frame Frame Frame 56 Zero Zero Zero Zero Zero Zero Zero Zero 64 abs minute abs minute abs minute abs minute abs minute abs minute abs minute abs minute 72 abs second abs second abs second abs second abs second abs second abs second abs second 80 abs frame abs frame abs frame abs frame abs frame abs frame abs frame abs frame Table 24 Output Register: Sub-code Q Data with CRC Flags Output (0xED) The cyclic redundancy code (CRC) is a set of flags that indicates the correctness of the 80bits of sub-code Q data. Note that the same data is output for both the DO0 and DO1 CRC flags. When sub-code Q data is included in the input data, the result of the CRC calculation can be read out along with the data. To read out the sub-code Q data, the data must be read out with INTQSY set as the E/INT interrupt output function, and the IC must be set up to output the load signal. When sub-code Q data is detected, the E/INT signal will output a high level or a high-level pulse. The sub-code Q data is updated on each rising edge on the E/INT signal. Applications must complete readout of this data within 13.3ms (standard speed) or 6.6ms (2 × speed) of the rising edge of the E/INT signal. CRC OUTPUT CONDITIONS L Errors were found in the sub-code Q data. H The sub-code Q data is correct. Table 25 CRC Flag Output |
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