WM8803CDTSLASHV datasheet(34/45 Pages) WOLFSON

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WM8803

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PP Rev 1.1 September 2003

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

FSSEL3

FSSEL2

FSSEL1

FSSEL0

FS4XIN

FLIMIT

GPIDAT

GPISEL

DI15

DI14

DI13

DI12

DI11

DI10

DI9

DI8

RDTMUT

RDTSTA

RDTSEL

OFSEL2

OFSEL1

Table 18 Input Register Function Settings 1: I/O Data Settings (0xE9)

GPISEL:

UGPI pin setting

0: Outputs the micro-controller interface register state. (initial value)

1: Outputs the clock switching transition period signal.

GPIDAT:

UGPI

pin setting

(Only valid when register output mode is set up)

0: Outputs the low level.

1: Outputs the high level. (initial value)

FLIMIT:

Input data reception limitation setting

0: No reception limitation. All data within the PLL locking range can be

received. (initial value)

1: Reception is limited. The input fs calculation result is reflected in the error

flag according to the FSSEL[3:0] setting.

FS4XIN:

Input fs calculation range setting

0: Perform fs calculation for input data in the range 32k to 96 kHz. (initial value)

1: Perform fs calculation for input data in the range 64k to 192 kHz.

FSSEL[3:0]:

Input data reception range setting

(When FLIMIT = “1” and FS4XIN = “0”)

0000: 32k, 44.1k, 48k, 64k, 88.2k, or 96kHz (initial value)

0001: 32kHz only

0010: 44.1kHz only

0011: 48kHz

0100: 88.2kHz only

0101: 96kHz only

0110: 44.1k or 88.2kHz only

0111: 48k or 96kHz only

1000: 32k or 44.1k or 48kHz

1001-1111:Reserved

WM8803CDT/V Datasheet(PDF) 34 Page - Wolfson Microelectronics plc

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