WM8803CDTSLASHV datasheet(24/45 Pages) WOLFSON

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WM8803

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PP Rev 1.1 September 2003

ERROR RECOVERY PROCESSING

When the preamble B, M, and W are detected, the PLL circuit goes to the locked state and data

demodulation starts. The SDATO output data starts on the first LRCLK edge after ERROR goes low.

SDATAO

Output starts from the LRCK edge immediately following the fall of the ERROR flag

ERROR

Internal clock signal

LRCLK

Data

15 ms to 50 ms

Figure 19 Data Processing at the Start of Data Demodulation

CHANNEL STATUS DATA

DATA DELIMITER BIT 1 OUTPUT ( AUDIO )

AUDIO

outputs the channel status bit 1, which indicates whether or not the input bi-phase data is

PCM audio data.

AUDIO

OUTPUT CONDITIONS

PCM audio data (CS bit 1 = low)

Non-PCM data (CS bit 1 = high)

Table 11 AUDIO Output

EMPHASIS INFORMATION OUTPUT (E/INT)

E/INT has a shared function as a micro-controller interface interrupt output or, in the initial settings

state, it outputs the presence or absence of emphasis of the input signal. This emphasis has a time

constant of 50/15µs for use in consumer products or broadcast studios.

E/INT

OUTPUT CONDITIONS

No pre-emphasis

50/15µs pre-emphasis

Table 12 E/INT Output

USER GENERAL PURPOSE INTERFACE OUTPUT PORT (

__________

UGPI

)

UGPI is a user-settable output port that supports the following functions.

—

Micro-controller interface register output

—

Clock switching transition period signal output

GPISEL selects between these functions. In the initial settings, the micro-controller interface register

GPIDAT is allocated to this pin. The initial setting of the GPIDAT register is 1, so a high level will be

output from UGPI .

WM8803CDT/V Datasheet(PDF) 24 Page - Wolfson Microelectronics plc

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