LTM4650 datasheet(32/138 Pages) AD

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conditions, the output voltage will drop from VINSn/2 by

RTH • ILOAD. In many applications, multi-layer ceramic

capacitors (MLCC) are selected as flying capacitors. The

voltage coefficients of MLCC capacitors strongly depend

on the type and size of capacitors. Normally larger size

X7R MLCC capacitors are better than X5R in terms of

voltage coefficient. The capacitance still drops 20% to

30% capacitance with high DC bias voltage. Capacitance

derating needs to be considered when estimating the out-

put resistance of the switched capacitor circuits.

UNDERVOLTAGE LOCKOUT

The LTM4664A divider stages have a precision UVLO

comparator constantly monitoring the INTVCCSn voltage

to ensure that an adequate gate drive voltage is present.

It locks out the switching action when INTVCCSn is below

4.9V. To prevent oscillation when there is a distuSrbance

on the INTVCCSn, the UVLO comparator has 200mV of

precision hysteresis. Another way to detect an under

voltage condition is to monitor the input supply. Because

the RUN pin has a precision turn-on reference of 1.22V,

one can use a resistor divider to the VINSn to turn on the

stage when the input voltage is high enough. An extra 5μA

of current flows out of the RUN pin once the RUNSn pin

voltage passes 1.22V. One can program the hysteresis

of the RUNSn comparator by adjusting the values of the

resistive divider.

FAULT RESPONSE AND TIMER PROGRAMMING

The LTM4664A divider stages stop switching and pull

the FAULTSn pins low during fault conditions. A capac-

itor connected from the TIMERSn pin to GND sets retry

time to start-up if fault conditions are removed. The typ-

ical waveform on TIMERSn pin during fault condition is

shown in Figure 7.

After the FAULTSn pin is pulled low, a 3.5μA pull-up current

flows out of TIMER pin and starts to charge the TIMERSn

capacitor. The pull-up current increases to 7μA when then

TIMERSn pin voltage is higher than 0.5V and back to

3.5μA when the TIMERSn pin voltage is higher than 1.2V.

The TIMERSn pin will be strongly pulled down whenever

the fault conditions are removed or the TIMERSn pin

voltage is higher than 4V. When the TIMERSn pin voltage

EFFECTIVE OPEN LOOP OUTPUT RESISTANCE AND

LOAD REGULATION

The LTM4664A divider stages do not regulate the output

voltage through a closed loop feedback system. However,

the output voltage is not sensitive to load conditions due

to the low output resistance when it is operating with

a certain quantity of flying capacitors and high switch-

ing frequency. The Thevenin equivalent circuit of voltage

divider circuit is shown in the Figure 6.

When duty cycle is around 50%:

ROUT =

1+e

–

S RDS(ON) C FLY

4fSCFLY 1–e

–

S RDS(ON)C FLY

⎛

⎝

⎜

⎞

⎠

⎟

Where:

fS is the switching frequency.

CFLY is the flying capacitor.

RDS(ON) is the on resistance of one MOSFET.

At low switching frequencies, RTH = 1/(4fS CFLY). As fre-

quency increases, the RTH will finally approach 2RDS(ON).

In high power applications, it is suggested to select the

switching frequency around 1/(16CFLY RDS(ON)) or higher

for decent load regulation and efficiency. At heavy load

LTM4664A

Rev. 0

For more information www.analog.com

4:1 DIVIDER APPLICATION INFORMATION

VIN

VIN/2

RTH

CFLY

CMID

SW1

SW3

MID

CMID

4664A F06

Figure 6.

LTM4650 Datasheet(PDF) 32 Page - Analog Devices

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