LTM4650 datasheet(23/138 Pages) AD

23 / 138 page

LTM4664A

Rev. 0

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PIN FUNCTIONS

FAULT_C0/FAULT_C1 (K10/K9): Digital Programmable

FAULT Inputs and Outputs. Open-drain output. A pull-up

resistor to 3.3V is required in the application.

VINS3_C1, VINS3_C0: (L1-L2, M1-M2), (L12-L13, M12-

M13): Main power input to channel 0, and channel 1

power stages. Provide sufficient decoupling capacitance

in the form of multilayer ceramic capacitors (MLCCs) and

low ESR electrolytic (or equivalent) to handle reflected

input current ripple from the step-down switching

stages. MLCCs should be placed as close to the VINS3

as physically possible. The VINS3_C1 input provides the

input power for the INTVCC LDO regulator. See Layout

Recommendations in the Dual 25A/30A PSM Applications

Information section.

VDD33 (L6): Internally Generated 3.3V Power Supply Output

Pin. This pin should only be used to provide external

current for the pull-up resistors required for FAULT_Cn,

SHARE_CLK, and SYNC, and may be used to provide exter-

nal current for pull-up resistors on RUN_Cn, SDA, SCL,

ALERT and PGOOD_Cn. No external decoupling is required.

SHARE_CLK (L7): Share_Clock, Bidirectional Open- Drain

Clock Sharing Pin. Nominally 100kHz. Used for synchro-

nizing the time base between multiple LTM4664As (and

any other Analog Devices products with a SHARE_ CLK

pin)—to realize well-defined rail sequencing and rail track-

ing. Tie the SHARE_CLK pins of all such devices together;

all devices with a SHARE_CLK pin will synchronize to the

fastest clock. A pull-up resistor to 3.3V is required.

SDA (L8): Serial Bus Data Open-Drain Input and Output.

A pull-up resistor to 3.3V is required in the application.

SCL (L9): Serial Bus Clock Open-Drain Input (Can Be an

Input and Output, if Clock Stretching is enabled). A pull-up

resistor to 3.3V is required in the application for digital

communication to the SMBus master(s) that nominally

drive this clock. The LTM4664A will never encounter sce-

narios where it would need to engage clock stretching

unless SCL communication speeds exceed 100kHz—and

even then, LTM4664A will not clock stretch unless clock

stretching is enabled by means of setting MFR_CONFIG_

ALL[1] = 1b. The factory-default NVM configuration set-

ting has MFR_CONFIG_ALL [1] = 0b: clock stretching

disabled. If communication on the bus at clock speeds

above 100kHz is required, the user’s SMBus master(s)

needs to implement clock stretching support to assure

solid serial bus communications, and only then should

MFR_CONFIG_ALL [1] be set to 1b. When clock stretch-

ing is enabled, SCL becomes a bidirectional, open-drain

output pin on LTM4664A.

TSNS_C0a, TSNS_C0b (L10 and T16, Respectively):

Channel 0 Temperature Excitation/Measurement and

Thermal Sensor Pins, respectively. Connect TSNS_C0a

to TSNS_C0b. This allows the LTM4664A to monitor the

Power Stage Temperature of Channel 0.

SYNC (M8): External Clock Synchronization Input and

Open-Drain Output Pin. If an external clock is present at

this pin, the switching frequency will be synchronized to

the external clock. If clock master mode is enabled, this

pin will pull low at the switching frequency with a 500ns

pulse to ground. A resistor pull-up to 3.3V is required in

the application if the LTM4664A is the master.

SGND_C0_C1 (M9, N8-N9): SGND_C0_C1 is the signal

ground return path of the dual 25A/30A control. SGND_C0_

C1 is not internally connected to GND. Connect SGND_C0_C1

to GND at the A9, B9, and C9 pins that is close to the output

capacitor ground connections. See recommended layout.

TSNS_C1a, TSNS_C1b (M10 and T1, Respectively):

Channel 1 Temperature Excitation/Measurement and

Thermal Sensor Pins, respectively. In most applica-

tions, connect TSNS_C1a to TSNS_C1b. This allows the

LTM4664A to monitor the Power Stage Temperature of

Channel 1. See the Applications section.

PWM_C0, PWM_C1 (M15, L4): PWM drive signal to

Channel 0, Channel 1 power stage. Utilized for debugging

or monitoring purposes.

PHFLT_C0, PHFLT_C1 (M16, L5): Thermal Warning for

Channel 0 and Channel 1. When the thermal protection

threshold is tripped, the PHFLT_Cn pin is being pulled

low. The power stage does not shut off, and is only a

thermal monitor. These pins are internally pulled up to

3.3V through 10k resistor. COMP_0b/COMP_1b (N10/

M7): Current Control Threshold and Error Amplifier

Compensation Nodes. Each associated channel’s current

comparator tripping threshold increases with its Comp

voltage. Each channel has a 22pF to SGND.

LTM4650 Datasheet(PDF) 23 Page - Analog Devices

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