Motor de Búsqueda de Datasheet de Componentes Electrónicos
  Mexican  ▼
ALLDATASHEET.COM.MX

X  

Preview PDF HTML

UPD17708 Datasheet(PDF) 321 Page - Renesas Technology Corp

No. de pieza UPD17708
Descripción Electrónicos  MOS INTEGRATED CIRCUIT
PDF  358 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD17708 Datasheet(HTML) 321 Page - Renesas Technology Corp

Back Button UPD17708 Datasheet HTML 317Page - Renesas Technology Corp UPD17708 Datasheet HTML 318Page - Renesas Technology Corp UPD17708 Datasheet HTML 319Page - Renesas Technology Corp UPD17708 Datasheet HTML 320Page - Renesas Technology Corp UPD17708 Datasheet HTML 321Page - Renesas Technology Corp UPD17708 Datasheet HTML 322Page - Renesas Technology Corp UPD17708 Datasheet HTML 323Page - Renesas Technology Corp UPD17708 Datasheet HTML 324Page - Renesas Technology Corp UPD17708 Datasheet HTML 325Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 321 / 358 page
background image
319
µPD17704, 17705, 17707, 17708, 17709
(2) Releasing from clock stop status
If the device is released from the backup status when supply voltage VDD is backed up at 2.2 V by using the
clock stop status, VDD must be raised to 3.5 V or more within tSET/2 after the clock stop status has been released
by INT pin interrupt or high level input to port 0D.
As shown in Figure 21-9, the device is released from the clock stop status by means of CE reset. However,
because the power-ON clear voltage is changed to 3.5 V tSET/2 after the clock stop status has been released,
power-ON reset is effected unless VDD is 3.5 V or higher.
The same applies when VDD is raised.
Figure 21-9. Releasing from Clock Stop Status
P0D
BTM0CY flag
setting pulse
XOUT
5 V
3.5 V
2.2 V
0 V
0 V
H
L
H
L
Power-ON
clear signal
H
L
Power-ON
clear voltage
Backup in clock stop
status
Halt status
tSET/2
Power-ON clear voltage changes
to 3.5 V at this point.
Therefore, VDD must be 3.5 V
or higher before this point.
Normal operation
Backup
STOP s instruction
H
VDD
Program starts
Power-ON clear voltage changes
to 2.2 V at this point.
Therefore, VDD must be 3.5 V
or higher before this point.
tSET: basic timer 0 setting time



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Descarga

Go To PDF Page


Enlace URL



¿ALLDATASHEET es útil para Ud.?  [ DONATE ] 

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Enlace a la hoja de datos    |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com