UPD17708 datasheet(59/358 Pages) RENESAS

59 / 358 page

µPD17704, 17705, 17707, 17708, 17709

6.3 Generating Address of General Register by Each Instruction

The following sections 6.3.1 and 6.3.2 explain how the address of the general register is generated when each

instruction is executed.

For the details of the operation of each instruction, refer to 7. ALU (Arithmetic Logic Unit) BLOCK.

6.3.1 Add (“ADD r, m”, “ADDC r, m”) ,

subtract (“SUB r, m”, “SUBC r, m”) ,

logical operation (“AND r, m”, “OR r, m”, “XOR r, m”),

direct transfer (“LD r, m”, “ST m, r”), and

rotation (“RORC r”) instructions

Table 6-1 shows the address of the general register specified by operand “r” of an instruction. Operand “r”

of an instruction specifies only a column address.

Table 6-1. Generating Address of General Register

6.3.2 Indirect transfer (“MOV @r, m”, “MOV m, @r”) instruction

Table 6-2 shows a general register address specified by instruction operand “r” and an indirect transfer

address specified by “@r”.

Table 6-2. Generating Address of General Register

6.4 Cautions on Using General Register

6.4.1 Row address of general register

Because the row address of the general register is specified by the general register pointer, the currently

specified bank may differ from the bank of the general register.

6.4.2 Operation between general register and immediate data

No instruction is available that executes an operation between the general register and immediate data.

To execute an operation between the general register and immediate data, the general register must be

treated as a data memory area.

General register address

Column address

Row address

Bank

Contents of general register pointer

General register address

Indirect transfer address

Column address

Row address

Bank

Contents of general register pointer

Contents of “r”

Same as data memory

UPD17708 Datasheet(PDF) 59 Page - Renesas Technology Corp