UPD17708 datasheet(88/358 Pages) RENESAS

No. de pieza	UPD17708

Descripción Electrónicos	MOS INTEGRATED CIRCUIT

PDF	358 Pages

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Fabricante Electrónico	RENESAS [Renesas Technology Corp]

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88 / 358 page

µPD17704, 17705, 17707, 17708, 17709

9.2 Data Buffer

9.2.1 Configuration of data buffer

Figure 9-2 shows the configuration of the data buffer.

As shown in the figure, the data buffer consists of a total of 16 bits of addresses 0CH through 0FH of BANK

0 on the data memory.

The 16-bit data is configured with bit 3 of address 0CH as the MSB and bit 0 of address 0FH as the LSB.

Because the data buffer is located on the data memory, it can be manipulated by all data memory manipulation

instructions.

Figure 9-2. Configuration of Data Buffer

Column address

234

BANK0

BANK1

BANK2

BANK14

BANK15

System register

Address

Bit

Signal

Data

b15

b14

b13

b12

DBF3

0CH

b11

b10

DBF2

0DH

DBF1

0EH

DBF0

0FH

Data memory

Data buffer

Remark

Data buffer (DBF)

Data memory

Data

The PD17704 and 17705 do

not have BANKs 6 through 14.

The PD17707 and 17705 do

not have BANKs 6 through 14.

UPD17708 Datasheet(PDF) 88 Page - Renesas Technology Corp

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