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UPD17708 Datasheet(PDF) 48 Page - Renesas Technology Corp |
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UPD17708 Datasheet(HTML) 48 Page - Renesas Technology Corp |
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48 / 358 page ![]() µPD17704, 17705, 17707, 17708, 17709 46 5.3 Address Register (AR) 5.3.1 Configuration of address register Figure 5-3 shows the configuration of the address register. As shown in the figure, the address register consists of 16 bits of system register addresses 74H through 77H (AR3 through AR0). Figure 5-3. Configuration of Address Register Address Name Symbol Bit Data 74H AR3 75H AR2 76H AR1 77H AR0 b3 M S B b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 L S B Power-ON reset WDT&SP reset CE reset Clock stop Address register (AR) 0 0 0 Retained 0 0 0 Retained 0 0 0 Retained 0 0 0 Retained Power-ON reset WDT&SP reset CE reset Clock stop : Reset by RESET pin on power application : Reset by watchdog timer and stack pointer : CE reset : On execution of clock stop instruction |
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