UPD17708 datasheet(67/358 Pages) RENESAS

67 / 358 page

µPD17704, 17705, 17707, 17708, 17709

8.2 Configuration and Function of Register File

Figure 8-2 shows the configuration of the register file and the relationships between the register file and data

memory.

The register file is assigned addresses in 4-bit units, like the data memory, and consists of a total of 128

nibbles with row addresses 0H through 7FH and column addresses 0H through 0FH.

Addresses 00H through 3FH are control registers that sets the conditions of the peripheral hardware units.

Addresses 40H through 7FH overlap the data memory.

In other words, addresses 40H through 7FH of the register file are addresses 40H through 7FH of the

currently-selected bank of data memory.

Because addresses 40H through 7FH of the register file overlap the same addresses of the data memory,

these addresses of the register file can be manipulated in the same manner as the data memory, except that

the addresses of the register file can also be manipulated by using register file manipulation instructions (“PEEK

WR, rf” and “POKE rf, WR”). Note, however, that addresses 60H through 6FH of BANK15 are assigned port

input/output selection registers (for details refer to 8.4 Port Input/Output Selection Registers).

Figure 8-2. Configuration of Register File and Relationship with Data Memory

Remark

The

µPD17704 and 17705 do not have BANKs 6 through 14.

The

µPD17707 and 17708 do not have BANKs 10 through 14.

Column address

789

System registers

Control registers

Data memory

BANK0

BANK1

BANK2

BANK14

BANK15

Port input/output selection registers

UPD17708 Datasheet(PDF) 67 Page - Renesas Technology Corp