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UPD17708 Datasheet(PDF) 241 Page - Renesas Technology Corp

No. de pieza UPD17708
Descripción Electrónicos  MOS INTEGRATED CIRCUIT
PDF  358 Pages
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD17708 Datasheet(HTML) 241 Page - Renesas Technology Corp

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µPD17704, 17705, 17707, 17708, 17709
<3> If forced wait is set after wait status has been released
Figure 16-15. Shift Clock Generation Timing in Serial I/O Mode (4/4)
Wait period
Wait released status
1/fSC
Forced wait by SIO0NWT
ab
Wait released
Wait period
Wait released status
a + b = 1/2fSC
a + b = 1/2fSC
1/fSC
Forced wait by SIO0NWT
ab
Wait released
<4> If wait status is released when it has been already released once
The clock output waveform is not affected. However, note that the clock counter is reset.
(8) Operations of SBSTT and SBBSY flags
The SBSTT and SBBSY flags operate only in the I2C bus mode.
These flags remain “0” in the serial I/O mode.



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