UPD17708 datasheet(260/358 Pages) RENESAS

260 / 358 page

258

µPD17704, 17705, 17707, 17708, 17709

(3) Pulse swallow mode (VHF)

In this mode, the VCOH pin is used.

The VCOL pin is pulled down.

In this mode, the swallow counter and programmable counter are used for frequency division.

(4) VCOL and VCOH pin disabled

In this mode, only the VCOL and VCOH pins are internally pulled down, but the other blocks operate.

17.2.3 Programmable divider and PLL data register

The programmable divider consists of a 5-bit swallow counter and a 12-bit programmable counter. Each counter

is a 17-bit binary down counter.

The programmable counter is allocated to the high-order 12 bits of the PLL data register, and the swallow counter

is allocated to the low-order 4 bits. Data are set to these counters via data buffer.

The least significant bit of the swallow counter sets data to the PLLSCNF flag of the control register.

The value by which the input signal frequency is to be divided is called “N value”.

For how to set a division value (N value) in each division mode, refer to 17.6 Using PLL Frequency Synthesizer.

(1) PLL data register and data buffer

Figure 17-4 shows the relationships between the PLL data register and data buffer.

In the direct division mode, the high-order 12 bits of the PLL data register are valid, and all 17 bits of the register

are valid in the pulse swallow mode.

In the direct division mode, all 12 bits are used as a programmable counter.

In the pulse swallow mode, the high-order 12 bits are used as a programmable counter, and the low-order 5

bits are used as a swallow counter.

(2) Relationship between division value N of programmable divider and divided output frequency

The relationship between the value “N” set to the PLL data register and the signal frequency “fN” divided and

output by the programmable divider is as shown below.

For details, refer to 17.6 Using PLL Frequency Synthesizer.

(a) Direct division mode (MF)

fIN =

fIN

N: 12 bits

(b) Pulse swallow mode (HF, VHF)

fIN =

fIN

N: 17 bits

UPD17708 Datasheet(PDF) 260 Page - Renesas Technology Corp