DSP56303 datasheet(65/292 Pages) FREESCALE

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Central Processor Unit (CPU) Registers

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

4-7

4.3.1 Status Register (SR)

The Status Register (SR) (Figure 4-1) is a 24-bit register that indicates the current system state of

the processor and the results of previous arithmetic computations. The SR is pushed onto the

system stack when program looping is initialized or a jsr is performed, including long interrupts.

The SR consists of the following three special-purpose 8-bit control registers:

Extended Mode Register (EMR) (SR[23–16]) and Mode Register (MR) (SR[15–8]).

These special-purpose registers define the current system state of the processor. The bits

in both registers are affected by hardware reset, exception processing, enddo (end current

do loop) instructions, rti (return from interrupt) instructions, and trap instructions. In

addition, the EMR bits are affected by instructions that specify SR as their destination (for

example, do forever instructions, brkcc instructions, and movec). During hardware reset,

all EMR bits are cleared. The MR register bits are affected by do instructions, and

instructions that directly reference the MR (for example, andi, ori, or instructions, such as

movec, that specify SR as the destination). During processor reset, the interrupt mask bits

are set and all other bits are cleared.

Condition Code Register (CCR) (SR[7–0]). Defines the results of previous arithmetic

computations. The CCR bits are affected by Data Arithmetic Logic Unit (Data ALU)

operations, parallel move operations, instructions that directly reference the CCR (for

example, ori and andi), and instructions that specify SR as a destination (for example,

movec). Parallel move operations affect only the S and L bits of the CCR. During

processor reset, all CCR bits are cleared.

The definition of the three 8-bit registers within the SR is primarily for the purpose of

compatibility with other Freescale DSPs. Bit definitions in the following paragraphs

identify the bits within the SR and not within the subregister.

Extended Mode Register (EMR)

Mode Register (MR)

Condition Code Register (CCR)

CP[1–0] RM SM CE

DM SC

S[1–0]

I[1–0]

Reset:

1000

00000

0000

1100

0000

Reserved bit. Read as zero; write to zero for future compatibility

Figure 4-1. Status Register (SR)

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