DSP56303 datasheet(91/292 Pages) FREESCALE

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Device Identification Register (IDR)

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

4-33

4.8 Device Identification Register (IDR)

The IDR is a read-only factory-programmed register that identifies DSP56300 family members.

It specifies the derivative number and revision number of the device. This information is used in

testing or by software. Figure 4-10 shows the contents of the IDR. Revision numbers are

assigned as follows: $0 is revision 0, $1 is revision A, and so on.

Figure 4-10. Identification Register Configuration (Revision E)

9–4

DAM

DMA Address Mode

Defines the address generation mode for the DMA transfer. These bits are encoded in two

different ways according to the D3D bit.

3–2

DDS[1–0]

DMA Destination Space

Specify the memory space referenced as a destination by the DMA.

Note:

In Cache mode, a DMA to Program memory space has some limitations (as

described in Chapter 3, Memory Configuration.

DDS1

DDS0

DMA Destination Memory Space

X Memory Space

Y Memory Space

P Memory Space

Reserved

1–0

DSS

DMA Source Space

Specify the memory space referenced as a source by the DMA.

Note:

In Cache mode, a DMA to Program memory space has some limitations (as

described in Chapter 3, Memory Configuration.

DSS1

DSS0

DMA Source Memory Space

X Memory Space

Y Memory Space

P Memory Space

Reserved

Revision Number

Derivative Number

$00

$303

Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued)

Bit

Number

Bit Name

Reset

Value

Description

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