DSP56303 datasheet(72/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

4-14

Freescale Semiconductor

Core Configuration

Cache Burst Mode Enable

Enables/disables Burst mode in the memory expansion port during an

instruction cache miss. If the bit is cleared, Burst mode is disabled and only

one program word is fetched from the external memory when an instruction

cache miss condition is detected. If the bit is set, Burst mode is enabled, and

up to four program words are fetched from the external memory when an

instruction cache miss is detected.

9–8

CDP[1–0]

Core-DMA Priority

Specify the priority of core and DMA accesses to the external bus.

Determined by comparing status register CP[1–0] to the active

DMA channel priority

DMA accesses have higher priority than core accesses

DMA accesses have the same priority as the core accesses

DMA accesses have lower priority than the core accesses

7MS0

Memory Switch Mode

Allows some internal data memory (X, Y, or both) to become part of the chip

internal Program RAM.

Notes: 1.

Program data placed in the Program RAM/Instruction Cache

area changes its placement after the OMR[MS] bit is set (that

is, the Instruction Cache always uses the highest internal

program RAM addresses).

To ensure proper operation, place six NOP instructions after

the instruction that changes the MS bit.

To ensure proper operation, do not set the MS bit while the

Instruction Cache is enabled (SR[CE] bit is set).

6SD0

Stop Delay Mode

Determines the length of the delay invoked when the core exits the Stop

state. The STOP instruction suspends core processing indefinitely until a

defined event occurs to restart it. If SD is cleared, a 128K clock cycle delay is

invoked before a STOP instruction cycle continues. However, if SD is set,

the delay before the instruction cycle continues is 16 clock cycles. The long

delay allows a clock stabilization period for the internal clock to begin

oscillating and to stabilize. When a stable external clock is used, the shorter

delay allows faster start-up of the DSP56300 core.

Reserved. Write to zero for future compatibility.

EBD

External Bus Disable

Disables the external bus controller to reduce power consumption when

external memories are not used. When EBD is set, the external bus

controller is disabled and external memory cannot be accessed. When EBD

is cleared, the external bus controller is enabled and external access can be

performed. Hardware reset clears the EBD bit.

3–0

MD–MA

Chip Operating Mode

Indicate the operating mode of the DSP56300 core. On hardware reset,

these bits are loaded from the external mode select pins, MODD, MODC,

MODB, and MODA, respectively. After the DSP56300 core leaves the Reset

state, MD–MA can be changed under program control.

* The MD–MA bits reflect the corresponding value of the mode input (that is, MODD–MODA), respectively.

Table 4-3. Operating Mode Register (OMR) Bit Definitions (Continued)

Bit Number

Bit Name

Reset Value

Description

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