DSP56303 datasheet(109/292 Pages) FREESCALE

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Operation

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

6-9

respectively. When host requests are enabled, the host request pins operate as shown in Figure

6-3.

Table 6-5 shows the operation of the HREQ pin when a single request line is used. The host can

test these ICR bits to determine the interrupt source.

Table 6-6 shows the operation of the transmit request (HTRQ) and receive request (HRRQ) lines

with dual host requests enabled.

6.4.5 Endian Modes

The Host Little Endian bit in the host-side Interface Control Register (ICR[5] = HLEND) allows

the host to access the HI08 data registers in Big Endian or Little Endian mode. In Little Endian

mode (HLEND = 1), a host transfer occurs as shown in Figure 6-4.

Figure 6-3. HI08 Host Request Structure

Table 6-5. HREQ Pin Operation In Single Request Mode (ICR[2] = HDRQ = 0)

ICR[1] = TREQ

ICR[0] = RREQ

HREQ Pin

No interrupts

RXDF request enabled

TXDE request enabled

RXDF and TXDE request enabled

Table 6-6. HTRQ and HRRQ Pin Operation In Double Request Mode (ICR[2] = HDRQ = 1)

ICR[1] = TREQ

ICR[0] = RREQ

HTRQ Pin

HRRQ Pin

No interrupts

RXDF request enabled

TXDE Request enabled

No interrupts

TXDE Request enabled

RXDF request enabled

HF1

HF0

HLEND TREQ RREQ ICR

Enable

INIT

Status

HF3

HF2

TRDY

TXDE RXDF ISR

HREQ

Host Request

Asserted

HRRQ

HREQ

HTRQ

Host Request

Signals

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