DSP56303 datasheet(123/292 Pages) FREESCALE

123 / 292 page

Host Programmer Model

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

6-23

Reserved. Write to 0 for future compatibility.

5HLEND

Host Little Endian

If the HLEND bit is cleared, the host can access the HI08 in Big-Endian byte

order. If set, the host can access the HI08 in Little-Endian byte order. If the

HLEND bit is cleared the RXH/TXH register is located at address $5, the

RXM/TXM register at $6, and the RXL/TXL register at $7. If the HLEND bit is

set, the RXH/TXH register is located at address $7, the RXM/TXM register at

$6, and the RXL/TXL register at $5.

4HF1

Host Flag 1

A general-purpose flag for host-to-DSP communication. The host processor

can set or clear HF1, and the DSP56303 can not change it. HF1 is reflected

in the HSR on the DSP side of the HI08.

3HF0

Host Flag 0

A general-purpose flag for host-to-DSP communication. The host processor

can set or clear HF0, and the DSP56303 cannot change it. HF0 is reflected in

the HSR on the DSP side of the HI08.

HDRQ

Double Host Request

If cleared, the HDRQ bit configures HREQ/HTRQ and HACK/HRRQ as

HREQ and HACK, respectively. If HDRQ is set, HREQ/HTRQ is configured

as HTRQ, and HACK/HRRQ is configured as HRRQ.

1TREQ

Transmit Request Enable

Enables host requests via the host request (HREQ or HTRQ) signal when the

transmit data register empty (TXDE) status bit in the ISR is set. If TREQ is

cleared, TXDE interrupts are disabled. If TREQ and TXDE are set, the host

request signal is asserted.

TREQ and RREQ modes (HDRQ = 0)

TREQ

RREQ

HREQ Signal

No interrupts (polling)

RXDF request (interrupt)

TXDE request (interrupt)

RXDF and TXDE request (interrupts)

TREQ and RREQ modes (HDRQ = 1)

TREQ

RREQ

HTRQ Signal

HRRQ Signal

No interrupts (polling)

No interrupts

(polling)

No interrupts (polling)

RXDF request

(interrupt)

TXDE request

(interrupt)

No interrupts

(polling)

TXDE request

(interrupt)

RXDF request

(interrupt)

RREQ

Receive Request Enable

Controls the HREQ signal for host receive data transfers. RREQ enables host

requests via the host request (HREQ or HRRQ) signal when the receive data

interrupts are disabled. If RREQ and RXDF are set, the host request signal

(HREQ or HRRQ) is asserted.

Table 6-15. Interface Control Register (ICR) Bit Definitions (Continued)

Bit Number

Bit Name

Reset Value

Description

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