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DSP56303 Datasheet(PDF) 194 Page - Freescale Semiconductor, Inc |
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DSP56303 Datasheet(HTML) 194 Page - Freescale Semiconductor, Inc |
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194 / 292 page  DSP56303 User’s Manual, Rev. 2 9-2 Freescale Semiconductor Triple Timer Module 9.1.2 Individual Timer Block Diagram Figure 9-2 shows the structure of an individual timer block. The DSP56303 treats each timer as a memory-mapped peripheral with four registers occupying four 24-bit words in the X data memory space. The three timers are identical in structure and function. Either standard polled or interrupt programming techniques can be used to service the timers. A single, generic timer is discussed in this chapter. Each timer includes the following: 24-bit counter 24-bit read/write Timer Control and Status Register (TCSR) 24-bit read-only Timer Count Register (TCR) 24-bit write-only Timer Load Register (TLR) 24-bit read/write Timer Compare Register (TCPR) Logic for clock selection and interrupt/DMA trigger generation. The timer mode is controlled by the TC[3–0] bits which are TCSR[7–4]. For a listing of the timer modes and descriptions of their operations, see Section 9.3, Operating Modes, on page 9-5. Figure 9-1. Triple Timer Module Block Diagram Timer Prescaler Count Register GDB 24 24 TPLR 24 Timer 0 Timer 2 Timer 1 24-bit Counter CLK/2 TIO0 TIO1 TIO2 TPCR Timer Prescaler Load Register 24 |
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