AFE4490 datasheet(21/85 Pages) TI2

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DATA[23:16]

DATA[15:8]

DATA[7:0]

R/W

ACK

NACK

SLAVE ADDRESS

ACK

REG ADDRESS

ACK

SLAVE ADDRESS

R/W

ACK

I2C_DAT

SA6

SA5

SA4

SA3

SA2

SA1

SA0

DATA[23:16]

DATA[15:8]

DATA[7:0]

ACK

R/W

I2C_DAT

Slave Address

AFE4404

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SBAS689D – JUNE 2015 – REVISED DECEMBER 2016

Product Folder Links: AFE4404

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With the previously mentioned protocols for data, start, and stop conditions in place, the write and read

operations are as shown in Figure 30 and Figure 31, respectively. In Figure 30 and Figure 31, the slave address

for the AFE (indicated as SA6 to SA0) is a 7-bit representation of address 58h. The R/W bit is the read/write bit

and is set to '1' for Read and '0' for Write. Only the ADC output registers (addressed from 2Ah to 2Fh) can be

read out without the need for setting the REG_READ bit. Prior to reading out any other register, the REG_READ

bit needs to be additionally set to '1'. In Figure 30 and Figure 31, the activity performed by the host is shown in

black whereas activity from the AFE is shown in red. Thus, after the host sends the slave address during a write

operation, the AFE pulls the I2C_DAT line low (shown as ACK) if the slave address matches 58h. Similarly, the

host pulls the I2C_DAT line high (shown as NACK) as acknowledgment of a successfully completed read

operation involving three bytes of data. Continuous read/write mode is not supported.

(1)

Activity performed by the host is shown in black whereas activity from the AFE is shown in red. Continuous read/write

mode is not supported.

Figure 30. I2C Write Option Timing

Figure 31. I2C Read Option Timing

8.3.6 Timing Engine

The AFE has a fully-integrated timing engine that can be programmed to generate all clock phases for

synchronized transmit drive, receive sampling, and data conversion. To enable the timing engine (after powering

up the device), enable the TIMEREN bit.

8.3.6.1 Timer and PRF Controls

The timing engine inside the AFE has a 16-bit counter. The duration of the count with respect to an internal clock

(the timer clock) determines the pulse repetition period. The pulse repetition frequency (PRF) can be set using

the PRPCT register bits that represent the high value of the counter (the low value of the counter is 0). The

counter automatically counts until reaching PRPCT and then returns to 0 to start the next count. To suspend the

count and keep the counter in reset state, enable the TM_COUNT_RST bit.

AFE4490 Datasheet(PDF) 21 Page - Texas Instruments

AFE4490 Datasheet(HTML) 21 Page - Texas Instruments

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