AFE4490 datasheet(7/85 Pages) TI2

7 / 85 page

AFE4404

www.ti.com

SBAS689D – JUNE 2015 – REVISED DECEMBER 2016

Product Folder Links: AFE4404

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(1)

PRF refers to the rate at which samples from each of the four phases are output from the AFE.

(2)

To extend the lower range of PRF down to 10 Hz, program the CLKDIV_PRF setting.

(3)

The effective bandwidth of the switched RC filter scales as a function of the sampling duty cycle. For example, at 2% sampling width

duty cycle, the effective bandwidth of the switched RC filter is approximately 50 Hz.

(4)

With appropriate setting of the clock divider ratio (CLKDIV_EXTMODE).

(5)

dBFS refers to a full-scale voltage of 2 V.

7.5 Electrical Characteristics

Minimum and maximum specifications are at TA = –20°C to 70°C, typical specifications are at 25°C. TX_SUP = 4 V, RX_SUP

= IO_SUP = 3 V, 100-Hz PRF, 8-MHz external clock (with CLKDIV_EXTMODE set to divide-by-2), detector CIN = 50 pF, and

CLKDIV_PRF set to 1, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PULSE REPETITION FREQUENCY

PRF(1)

Pulse repetition frequency

10(2)

1000

SPS

RECEIVER

Offset cancellation DAC current range

–7 to 7

µA

Offset cancellation DAC current step

0.47

µA

TIA gain setting

10k to 2M

Cf setting

2.5 to 25

Switched RC filter bandwidth

2.5(3)

kHz

ADC averages

Detector capacitance

Differential capacitance between INP, INN

200

TRANSMITTER

LED current range

ILED_2X = 0

0 to 50

ILED_2X = 1

0 to 100

LED current resolution

Bits

CLOCKING (Internal Oscillator)

Frequency

MHz

Accuracy

Room temperature

±1%

Frequency drift with temperature

Full temperature range

±0.5%

Jitter (RMS)

100

Output clock high level

IO_SUP

Output clock low level

Output clock rise and fall times

10% to 90%, 15-pF load capacitance on

CLK pin

< 30

CLOCKING (External Clock)

Frequency range(4)

MHz

Input clock high level

IO_SUP

Input clock low level

Input capacitance of CLK pin

Capacitance to ground

< 4

I2C INTERFACE

Maximum clock speed

400

kHz

I2C slave address

Hex

PERFORMANCE

Receiver SNR

SNR over a 20-Hz bandwidth for a 500-kΩ

gain setting, 50% FS output, 2% LED and

sampling pulse duration,

ADC averages set to 16

100

dBFS(5)

Transmitter SNR

SNR over a 20-Hz bandwidth for a 50-mA

LED current setting

100

dBFS(5)

AFE4490 Datasheet(PDF) 7 Page - Texas Instruments

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