AFE4490 datasheet(72/85 Pages) TI2

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AFE4404

SBAS689D – JUNE 2015 – REVISED DECEMBER 2016

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Typical Application (continued)

Figure 4 illustrates the SNR plots corresponding to the same data as Figure 3. The input-referred noise and SNR

can be related as follows: the input-referred noise current can be first referred to the receiver output using a

factor of 2Rf, where Rf is 500 kΩ for this case. This output-referred voltage gives the output noise that can then

be referred to the full-scale value of 2 V (note that when the full-scale differential input to the ADC is 2.4 VPP, the

operating range is 2 VPP, which is the valid operating range of the TIA).

Figure 5 plots the input-referred noise current versus sampling duty cycle across different TIA gain settings.

Figure 6 corresponds to the SNR plot of the data in Figure 5. As illustrated in Figure 5, a dynamic range of 100

dB or more can be achieved in the receiver for many of the TIA gain settings. A reduction in SNR for higher TIA

gain settings is in line with what is expected from the receiver because a higher TIA gain setting implies a lower

signal level at the input of the receiver.

Figure 7 and Figure 8 correspond to the input-referred noise current and corresponding SNR across the

sampling duration duty cycle for different settings of the ADC averaging (as set by the NUMAV register setting).

An ADC averaging of 1 implies no averaging. As illustrated in these curves, the SNR improves with averaging

more samples. This improvement becomes more pronounced at lower TIA gain settings where the ADC noise

has a higher affect on the overall receiver noise.

The input-referred current noise current versus sampling duty cycle for different decimation factors is illustrated in

Figure 9. As illustrated in Figure 9, a 4X decimation leads to almost a 2X reduction in input-referred noise.

Figure 10 refers to a hypothetical case that is used to illustrate the improvement in the receiver dynamic range

when using the offset cancellation DAC. Assume that the dc level of the signal current corresponds to 7.25 µA.

Without the offset cancellation DAC, assume operation is with a TIA gain of 25 kΩ, which causes the output of

the receiver to be at 362.5 mV. If the offset cancellation DAC is enabled with a subtraction current of 7 µA (the

maximum setting), then the signal level at the input of the TIA after the offset cancellation DAC subtraction is

0.25 µA. For this current, a TIA gain setting of 1 MΩ causes the TIA output to be at 500 mV. In effect, by

enabling the offset cancellation DAC with the right setting, a higher TIA gain setting is allowed, which ends up

reducing the contribution of the ADC noise and thereby reduces the input-referred noise current of the receiver.

Note that the benefit from the offset cancellation DAC may not be so dramatic in an actual use case because

perfect cancellation of the dc signal may not be achieved from the 0.5-µA resolution of the offset cancellation

DAC. Even if achieved, the highest possible TIA gain setting on the residual current may cause receiver

saturation with small changes in the dc signal level. For this reason, a safe value for the maximum gain setting

when operating with the offset cancellation DAC is 250 kΩ or less. The third curve in Figure 10 illustrates this

case.

Figure 11 illustrates the effective response of the switched RC filter at the receiver output. The switched RC filter

has a physical RC time constant that corresponds to a bandwidth of approximately 2.5 kHz. However, the

effective bandwidth of the filter scales approximately with the sampling duration duty cycle. For a lower duty

cycle, the effective filter bandwidth reduces as described from the comparison of a 5% duty cycle with a 25%

duty cycle. At even lower duty cycles, the filter can double-up as a noise bandwidth reduction filter that can relax

the digital-filtering requirements in the MCU.

Figure 12 illustrates the switched RC filter response for a sampling duty cycle of 1% across different PRF

settings.

Figure 13 illustrates the switched RC filter response for a sampling duty cycle of 5% across different PRF

settings.

Figure 14 illustrates the LED current value versus the LED current setting code. The mode marked as 50-mA

LED Current Mode corresponds to the default setting of ILED_2X = 0, whereas the mode marked as 100-mA

LED Current Mode corresponds to ILED_2X = 1. The ideal slope of these curves corresponds to 0.793 mA per

code for the 50-mA current mode and 1.587 mA per code for the 100-mA current mode. However, a small

deviation from these ideal values can exist from device to device, and can be viewed as a gain error in the LED

current versus code. This deviation can be larger for the 100-mA current mode, with slight saturation of current

especially at the high-current settings.

AFE4490 Datasheet(PDF) 72 Page - Texas Instruments

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