AFE4490 datasheet(5/85 Pages) TI2

5 / 85 page

AFE4404

www.ti.com

SBAS689D – JUNE 2015 – REVISED DECEMBER 2016

Product Folder Links: AFE4404

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(1)

Depending on whether external clock mode or internal oscillator mode is used, extra series or shunt resistors are recommended on the

CLK pin. For more details, see the Typical Application section.

(2)

In both hardware power-down (PWDN) and software power-down (PDNAFE) modes, the CLK pin is driven by the AFE to 0 V.

Therefore, if operating in external clock mode, take care to shut off the external clock to the AFE when in these power-down modes.

(3)

Maintain the indicated polarity of photodiode connections to the AFE input pins.

(4)

A RESET pulse must be applied after power-up to ensure that the registers are all reset to their default values.

Pin Functions

I/O

DESCRIPTION

NAME

NO.

ADC_RDY

Digital

ADC ready interrupt signal (output)

CLK

Digital

Clock input or output, selectable based on register. Default is input (external clock mode).

Can be set via a register to output the clock when the oscillator is enabled.(1)(2)

DNC

Do not connect (leave floating)

GND

Ground

Common ground for transmitter and receiver

I2C_CLK

Digital

I2C clock input, external pullup resistor to IO_SUP (for example, 10 kΩ)

I2C_DAT

Digital

I2C data, external pullup resistor to IO_SUP (for example, 10 kΩ)

INM

Analog

Connect only to anode of photodiode(3)

INP

Analog

Connect only to cathode of photodiode(3)

IO_SUP

Supply

Separate supply for digital I/O. Must be less than or equal to RX_SUP.

Can be tied to RX_SUP.

RESETZ

Digital

RESETZ or PWDN: function based on (active low) duration of RESETZ pulse(4).

A 25-µs to 50-µs duration = RESETZ active.

A > 200-µs duration = PWDN active.

RX_SUP

Supply

Receiver supply; 1-µF decapacitor to GND

TX1

Analog

Transmit output, LED1

TX2

Analog

Transmit output, LED2

TX3

Analog

Transmit output, LED3

TX_SUP

Supply

Transmitter supply; 1-µF decapacitor to GND

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