AFE4490 datasheet(9/85 Pages) TI2

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Duty Cycle (%)

100

200

500

1000

2000

5000

10000

20000

50000

100000

Rf = 10 k:

Rf = 25 k:

Rf = 50 k:

Rf = 100 k:

Rf = 250 k:

Rf = 500 k:

Rf = 1000 k:

Rf = 2000 k:

Duty Cycle (%)

100

102

104

106

108

Rf = 10 k:

Rf = 25 k:

Rf = 50 k:

Rf = 100 k:

Rf = 250 k:

Rf = 500 k:

Rf = 1000 k:

Rf = 2000 k:

Duty Cycle (%)

Output Voltage = 0% of FS

Output Voltage = 10% of FS

Output Voltage = 25% of FS

Output Voltage = 50% of FS

Output Voltage = 75% of FS

Duty Cycle (%)

100

102

104

106

Output Voltage = 0% of FS

Output Voltage = 10% of FS

Output Voltage = 25% of FS

Output Voltage = 50% of FS

Output Voltage = 75% of FS

External Clock Frequency (MHz)

550

650

750

850

950

1050

1150

1250

CLKDIV_EXTMODE = 1

CLKDIV_EXTMODE = 2

CLKDIV_EXTMODE = 3

CLKDIV_EXTMODE = 4

CLKDIV_EXTMODE = 6

CLKDIV_EXTMODE = 8

CLKDIV_EXTMODE = 12

PRF (Hz)

200

400

600

800

1000

1200

1400

100

200

300

400

500

600

700

800

900

CLKDIV_PRF = 1

CLKDIV_PRF = 16

AFE4404

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SBAS689D – JUNE 2015 – REVISED DECEMBER 2016

Product Folder Links: AFE4404

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7.7 Typical Characteristics

At 25°C, TX_SUP = 4 V, RX_SUP = IO_SUP = 3.3 V, 100-Hz PRF, 25% duty cycle, Rf = 500 kΩ, Cf is adjusted to keep the

TIA time constant at 1/10th of the sampling duration, 8-MHz external clock (with CLKDIV_EXTMODE set to divide-by-2),

CLKDIV_PRF = 1, detector CIN = 50 pF, ADC averaging = max allowed, SNR (dBFS) = noise referred to full-scale range of

2 V, noise integrated from 1 Hz to Nyquist (= PRF / 2), and values assigned to CLKDIV_EXTMODE and CLK_DIV_PRF

parameters correspond to division ratios controlled by these modes, unless otherwise specified.

Figure 1. Receiver Current vs External Clock Frequency

Active window = 500 µs, LED pulse = 100 µs,

all four DYNAMIC bits set to 1

Figure 2. Receiver Current vs PRF in

Dynamic Power-Down Mode

Duty cycle (x-axis) refers to the sampling duration expressed as a

percentage of the pulse repetition period.

Figure 3. Input-Referred Noise Current in 20-Hz Bandwidth

vs Duty Cycle for Different Output Levels

(As a Percentage of Full-Scale)

Duty cycle (x-axis) refers to the sampling duration expressed as a

percentage of the pulse repetition period.

Figure 4. Signal-to-Noise Ratio in 20-Hz Bandwidth vs Duty

Cycle for Different Output Levels

(As a Percentage of Full-Scale)

Figure 5. Receiver Input-Referred Noise Current in 20-Hz

BW vs Duty Cycle (Different TIA Gain Settings)

Figure 6. Receiver SNR in 20-Hz BW vs Duty Cycle

(Different TIA Gain Settings)

AFE4490 Datasheet(PDF) 9 Page - Texas Instruments

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