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TPL0102 Datasheet(PDF) 7 Page - Texas Instruments

No. de pieza TPL0102
Descripción Electrónicos  TPL0102 Two 256-Taps Digital Potentiometers With Non-Volatile Memory
PDF  48 Pages
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Fabricante Electrónico  TI2 [Texas Instruments]
Página de inicio  https://www.ti.com
Logo TI2 - Texas Instruments

TPL0102 Datasheet(HTML) 7 Page - Texas Instruments

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TPL0102
www.ti.com
SLIS134C – MARCH 2011 – REVISED SEPTEMBER 2015
Product Folder Links: TPL0102
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Operating Characteristics (continued)
VDD = 2.7 V to 5.5 V, VSS = 0 V, VH = VDD, VL = GND, TA = –40°C to 85°C (unless otherwise noted). Typical values are at
VDD = 5 V, TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I2C Interface Specifications
VIH
Input high voltage
0.7 x VDD
5.5
V
VIL
Input low voltage
0
0.3 x VDD
V
VOL
Output low voltage
SDA pin, IOL = 4 mA
0.4
V
CIN
Pin capacitance
A0, A1, A2, SDA, SCL pins
7
pF
(1)
Cb = total capacitance of one bus line in pF
6.7 Timing Requirements
VDD = 2.7 V to 5.5 V, VSS = 0 V, VH = VDD, VL = GND, TA = –40°C to 85°C (unless otherwise noted). Typical values are at VDD
= 5 V, TA = 25°C (unless otherwise noted).
STANDARD
MODE I2C BUS
FAST
MODE I2C BUS
UNIT
MIN
MAX
MIN
MAX
I2C Interface Timing Requirements
fSCL
I2C clock frequency
0
100
0
400
kHz
tSCH
I2C clock high time
4
0.6
µs
tSCL
I2C clock low time
4.7
1.3
µs
tsp
I2C spike time
0
50
0
50
ns
tSDS
I2C serial data setup time
250
100
ns
tSDH
I2C serial data hold time
0
0
ns
tICR
I2C input rise time
1000
20 + 0.1Cb
(1)
300
ns
tICF
I2C input fall time
300
20 + 0.1Cb
(1)
300
ns
tICF
I2C output fall time, 10 pF to 400 pF bus
300
20 + 0.1Cb
(1)
300
ns
tBUF
I2C bus free time between stop and start
4.7
1.3
µs
tSTS
I2C start or repeater start condition setup time
4.7
1.3
µs
tSTH
I2C start or repeater start condition hold time
4
0.6
µs
tSPS
I2C stop condition setup time
4
0.6
µs
tVD(DATA)
Valid data time, SCL low to SDA output valid
1
1
µs
3tVD(ACK)
Valid data time of ACK condition, ACK signal from SCL
low to SDA (out) low
1
1
µs



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