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PSD835G2 Datasheet(PDF) 67 Page - STMicroelectronics

No. de pieza PSD835G2
Descripción Electrónicos  Configurable Memory System on a Chip for 8-Bit Microcontrollers
PDF  110 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD835G2 Datasheet(HTML) 67 Page - STMicroelectronics

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PSD8XX Family
PSD835G2
66
APD EN
PMMR0 BIT 1=1
ALE
RESET
CSI
CLKIN
TRANSITION
DETECTION
EDGE
DETECT
APD
COUNTER
POWER DOWN
(PDN)
DISABLE BUS
INTERFACE
SECONDARY
FLASH SELECT
MAIN FLASH SELECT
SRAM SELECT
PD
CLR
PD
DISABLE MAIN AND
SECONDARY FLASH/SRAM
PLD
SELECT
Figure 29. APD Logic Block
The
PSD835G2
Functional
Blocks
(cont.)
Enable APD
Set PMMR0 Bit 1 = 1
PSD in Power
Down Mode
ALE/AS idle
for 15 CLKIN
clocks?
RESET
Yes
No
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 0.
Figure 30. Enable Power Down Flow Chart



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