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PSD835G2 Datasheet(PDF) 93 Page - STMicroelectronics

No. de pieza PSD835G2
Descripción Electrónicos  Configurable Memory System on a Chip for 8-Bit Microcontrollers
PDF  110 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD835G2 Datasheet(HTML) 93 Page - STMicroelectronics

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PSD8XX Family
PSD835G2
92
-90
-12
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
tWLQV (PF)
WR to Data Propagation Delay
(Note 2)
40
43
ns
tDVQV (PF)
Data to Port F Data Propagation
Delay
(Note 5)
35
38
ns
tWHQZ (PF)
WR Invalid to Port F Tri-state
(Note 2)
33
33
ns
Port F Peripheral Data Mode Write Timing (3.0 V to 3.6 V Versions)
Microcontroller Interface – PSD835G2 AC/DC Parameters
(3.0 V to 3.6 V Versions)
NOTES: 1. RD timing has the same timing as DS and PSEN signals.
2. WR timing has the same timing as E and DS signals.
3. Any input used to select Port F Data Peripheral Mode.
4. Data is already stable on Port F.
5. Data stable on ADIO pins to data on Port F.
-90
-12
Turbo
Symbol
Parameter
Conditions
Min
Max
Min
Max
Off
Unit
tAVQV (PF)
Address Valid to Data Valid
(Note 3)
50
50
Add 20
ns
tSLQV (PF)
CSI Valid to Data Valid
35
40
Add 20
ns
RD to Data Valid
(Notes 1 and 4)
35
40
ns
tRLQV (PF)
RD to Data Valid, 8031 Mode
45
45
ns
tDVQV (PF)
Data In to Data Out Valid
34
38
ns
tQXRH (PF)
RD Data Hold Time
0
0
ns
tRLRH (PF)
RD Pulse Width
(Note 1)
35
36
ns
tRHQZ (PF)
RD to Data High-Z
(Note 1)
38
40
ns
Port F Peripheral Data Mode Read Timing (3.0 V to 3.6 V Versions)



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