PSD835G2 datasheet(58/110 Pages) STMICROELECTRONICS

No. de pieza	PSD835G2

Descripción Electrónicos	Configurable Memory System on a Chip for 8-Bit Microcontrollers

PDF	110 Pages

Scroll/Zoom	100%

Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

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58 / 110 page

PSD835G2

PSD8XX Family

The

PSD835G2

Functional

Blocks

(cont.)

PSEL0

PSEL1

PSEL

VM REGISTER BIT 7

PF0 - PF7

D0-D7

DATA BUS

Figure 25. Peripheral I/O Mode

9.4.3 Port Configuration Registers (PCRs)

Each port has a set of PCRs used for configuration. The contents of the registers can be

accessed by the microcontroller through normal read/write bus cycles at the addresses

given in Table 6. The addresses in Table 6 are the offsets in hex from the base of the

CSIOP register.

The pins of a port are individually configurable and each bit in the register controls its

respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three PCRs,

shown in Table 22, are used for setting the port configurations. The default power-up state

for each register in Table 19 is 00h.

Port

MCU Access

Control

E,F,G

Write/Read

Direction

A,B,C,D,E,F,G

Write/Read

Drive Select*

A,B,C,D,E,F,G

Write/Read

Table 19. Port Configuration Registers

*NOTE: See Table 26 for Drive Register bit definition.

PSD835G2 Datasheet(PDF) 58 Page - STMicroelectronics