MPC8377ECVRALDA datasheet(109/124 Pages) FREESCALE

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MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

109

Clocking

23.2

Core PLL Configuration

RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300

core clock (core_clk). Table 78 shows the encodings for RCWL[COREPLL]. COREPLL values that are

not listed in Table 78 should be considered as reserved.

NOTE

Core VCO frequency = core frequency

× VCO divider

VCO divider has to be set properly so that the core VCO frequency is in the

range of 800–1600 MHz.

Low

0110

6 : 1

150

200

Low

0111

7 : 1

175

233

Low

1000

8 : 1

200

266

Low

1001

9 : 1

225

300

Low

1010

10 : 1

250

333

Low

1011

11 : 1

275

Low

1100

12 : 1

300

Low

1101

13 : 1

325

Low

1110

14 : 1

Low

1111

15 : 1

CFG_CLKIN_DIV doubles csb_clk if set high.

CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.

Table 78. e300 Core PLL Configuration

RCWL[COREPLL]

core_clk : csb_clk Ratio

VCO Divider 1

0–1

2–5

0000

PLL bypassed

(PLL off,

csb_clk clocks

core directly)

PLL bypassed

(PLL off,

csb_clk clocks

core directly)

nnnn

nn/a

n/a

0001

01:1

0001

01:1

0001

01:1

Table 77. CSB Frequency Options for Agent Mode (continued)

CFG_CLKIN_DIV

at reset 1

SPMF

csb_clk :

Input Clock

Ratio 2

Input Clock

Frequency (MHz) 2

33.33

66.67

csb_clk

Frequency (MHz)

—

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