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PCIMX515CJM6C Datasheet(PDF) 36 Page - Freescale Semiconductor, Inc |
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PCIMX515CJM6C Datasheet(HTML) 36 Page - Freescale Semiconductor, Inc |
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36 / 184 page  i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 36 Freescale Semiconductor Preliminary—Subject to Change Without Notice Electrical Characteristics 3.6 Module Timing This section contains the timing and electrical parameters for the modules in the i.MX51 processor. 3.6.1 Reset Timings Parameters Figure 10 shows the reset timing and Table 32 lists the timing parameters. Figure 10. Reset Timing Diagram 3.6.2 WDOG Reset Timing Parameters Figure 11 shows the WDOG reset timing and Table 33 lists the timing parameters. Figure 11. WATCHDOG_RST Timing Diagram NOTE CKIL is approximately 32 kHz. TCKIL is one period or approximately 30 μs. 3.6.3 AUDMUX Timing Parameters The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of AUDMUX external pins is hence governed by the SSI module. Table 32. Reset Timing Parameters ID Parameter Min Max Unit CC1 Duration of RESET_IN to be qualified as valid (input slope = 5 ns) 50 — ns Table 33. WATCHDOG_RST Timing Parameters ID Parameter Min Max Unit CC5 Duration of WATCHDOG_RESET Assertion 1 — TCKIL RESET_IN CC1 (Input) WATCHDOG_RST CC5 (Input) |
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