PCIMX515CJM6C datasheet(70/184 Pages) FREESCALE

70 / 184 page

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Electrical Characteristics

3.7.6.1

Standard and Fast Mode Timing Parameters

Figure 44 depicts the standard and fast mode timings of HS-I2C module, and Table 62 lists the timing

characteristics.

Figure 44. HS-I2C Standard and Fast Mode Bus Timing

Table 62. HS-I2C Timing Parameters—Standard and Fast Mode

Parameter

Standard Mode

Fast Mode

Unit

Min

Max

Min

Max

IC1

SCLH cycle time

—

2.5

—

µs

IC2

Hold time (repeated) START condition

4.0

—

0.6

—

µs

IC3

Set-up time for STOP condition

4.0

—

0.6

—

µs

IC4

Data hold time

1 A device must internally provide a hold time of at least 300 ns for SDAH signal in order to bridge the undefined region of the

falling edge of SCLH.

3.452

2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC6) of the SCLH signal

0.92

µs

IC5

HIGH Period of SCLH Clock

4.0

—

0.6

—

µs

IC6

LOW Period of the SCLH Clock

4.7

—

1.3

—

µs

IC7

Set-up time for a repeated START condition

4.7

—

0.6

—

µs

IC8

Data set-up time

250

—

1003

3 A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC8)

of 250 ns must then be met. This automatically is the case if the device does not stretch the LOW period of the SCLH signal.

If such a device does stretch the LOW period of the SCLH signal, it must output the next data bit to the SDAH line max_rise_time

(ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)

before the SCLH line is released.

—ns

IC9

Bus free time between a STOP and START condition

4.7

—

1.3

—

µs

IC10

Rise time of both SDAH and SCLH signals

—

1000

20+0.1Cb

4 C

b = total capacitance of one bus line in pF.

300

IC11

Fall time of both SDAH and SCLH signals

—

300

20+0.1Cb

300

IC12

Capacitive load for each bus line (Cb)

—

100

—

100

IC10

IC11

IC9

IC2

IC8

IC4

IC7

IC3

IC6

IC10

IC5

IC11

START

STOP

START

SDAH

SCLH

IC1

PCIMX515CJM6C Datasheet(PDF) 70 Page - Freescale Semiconductor, Inc

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