PCIMX515CJM6C datasheet(63/184 Pages) FREESCALE

63 / 184 page

Electrical Characteristics

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

3.7.2

eCSPI Timing Parameters

This section describes the timing parameters of the eCSPI. The eCSPI has separate timing parameters for

master and slave modes. The nomenclature used with the CSPI modules and the respective routing of these

signals is shown in Table 51 on page 61.

3.7.2.1

eCSPI Master Mode Timing

Figure 35 depicts the timing of eCSPI in Master mode and Table 52 lists the eCSPI Master Mode timing

characteristics.

Figure 37. eCSPI Master Mode Timing Diagram

Table 54. eCSPI Master Mode Timing Parameters

Parameter

Symbol

Min

Max

Unit

CS1

eCSPIx_CLK Cycle Time–Read

eCSPIx_CLK Cycle Time–Write

tclk

—ns

CS2

eCSPIx_CLK High or Low Time

tSW

6—

CS3

eCSPIx_CLK Rise or Fall

tRISE/FALL

——

CS4

eCSPIx_CS_x pulse width

tCSLH

—

CS5

eCSPIx_CS_x Lead Time (CS setup time)

tSCS

5—

CS6

eCSPIx_CS_x Lag Time (CS hold time)

tHCS

5—

CS7

eCSPIx_DO Setup Time

tSmosi

5—

CS8

eCSPIx_DO Hold Time

tHmosi

5—

CS9

eCSPIx_DI Setup Time

tSmiso

5—

CS10

eCSPIx_DI Hold Time

tHmiso

5—

CS11

eCSPIx_DRYN Setup Time

tSDRY

5—

CS1

CS7 CS8

CS2

CS4

CS6

CS5

CS9 CS10

eCSPIx_CLK

eCSPIx_CS_x

eCSPIx_DO

eCSPIx_DI

eCSPIx_DRYN1

CS11

CS3

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