PCIMX515CJM6C datasheet(74/184 Pages) FREESCALE

74 / 184 page

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Electrical Characteristics

A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the

corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is

valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.

SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops

receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the

SENSB_VSYNC timing repeats.

3.7.8.1.3

Non-Gated Clock Mode

The timing is the same as the gated-clock mode (described in Section 3.7.8.1.2, “Gated Clock Mode”),

except for the SENSB_HSYNC signal, which is not used. See Figure 48. All incoming pixel clocks are

valid and cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states

low) until valid data is going to be transmitted over the bus.

Figure 48. Non-Gated Clock Mode Timing Diagram

The timing described in Figure 48 is that of a typical sensor. Some other sensors may have a slightly

different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC;

active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.

3.7.8.2

Electrical Characteristics

Figure 49 depicts the sensor interface timing. SENSB_MCLK signal described here is not generated by

the IPU.

Figure 49. Sensor Interface Timing Diagram

SENSB_VSYNC

SENSB_PIX_CLK

SENSB_DATA[19:0]

invalid

1st byte

n+1th frame

invalid

1st byte

nth frame

Start of Frame

IP3

SENSB_DATA,

SENSB_VSYNC,

IP2

1/IP1

SENSB_PIX_CLK

(Sensor Output)

SENSB_HSYNC

PCIMX515CJM6C Datasheet(PDF) 74 Page - Freescale Semiconductor, Inc

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