PCIMX515CJM6C datasheet(73/184 Pages) FREESCALE

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Electrical Characteristics

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

3.7.8

Image Processing Unit (IPU) Module Parameters

The purpose of the IPU is to provide comprehensive support for the flow of data from an image sensor

and/or to a display device. This support covers all aspects of these activities:

•

Connectivity to relevant devices—cameras, displays, graphics accelerators, and TV encoders.

•

Related image processing and manipulation: sensor image signal processing, display processing,

image conversions, and other related functions.

•

Synchronization and control capabilities such as avoidance of tearing artifacts.

3.7.8.1

Sensor Interface Timings

There are three camera timing modes supported by the IPU.

3.7.8.1.1

BT.656 and BT.1120 Video Mode

Smart camera sensors, which include imaging processing, usually support video mode transfer. They use

an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing

syntax is defined by the BT.656/BT.1120 standards.

This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only

control signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data

stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital blanking

is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding from the data

stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use. On BT.656 one

component per cycle is received over the SENSB_DATA bus. On BT.1120 two components per cycle are

received over the SENSB_DATA bus.

3.7.8.1.2

Gated Clock Mode

The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See

Figure 47.

Figure 47. Gated Clock Mode Timing Diagram

SENSB_VSYNC

SENSB_HSYNC

SENSB_PIX_CLK

SENSB_DATA[19:0]

invalid

1st byte

n+1th frame

invalid

1st byte

nth frame

Active Line

Start of Frame

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