PCIMX515CJM6C datasheet(111/184 Pages) FREESCALE

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Electrical Characteristics

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

Freescale Semiconductor

111

Preliminary—Subject to Change Without Notice

Figure 77. UDMA In Device Terminates Transfer Timing Diagram

Table 82. UDMA In Burst Timing Parameters

ATA

Parameter

from

Figure 75,

Figure 76,

Figure 77

Description

Controlling Variable

tack

tack (min) = (time_ack

× T) – (tskew1 + tskew2)

time_ack

tenv

tenv (min) = (time_env

× T) – (tskew1 + tskew2)

tenv (max) = (time_env

× T) + (tskew1 + tskew2)

time_env

tds

tds1

tds – (tskew3) – ti_ds > 0

tskew3, ti_ds, ti_dh

should be low enough

tdh

tdh1

tdh – (tskew3) – ti_dh > 0

tcyc

tc1

(tcyc – tskew) > T

T big enough

trp

trp (min) = time_rp

× T – (tskew1 + tskew2 + tskew6)

time_rp

—tx11

1 There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last

active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.

(time_rp

× T) – (tco + tsu + 3T + 2 ×tbuf + 2×tcable2) > trfs (drive)

time_rp

tmli

tmli1

tmli1 (min) = (time_mlix + 0.4)

× T

time_mlix

tzah

tzah (min) = (time_zah + 0.4)

× T

time_zah

tdzfs

tdzfs = (time_dzfs

× T) – (tskew1 + tskew2)

time_dzfs

tcvh

tcvh = (time_cvh

×T) – (tskew1 + tskew2)

time_cvh

—ton

toff2

2 Make ton and toff big enough to avoid bus contention.

ton = time_on

× T – tskew1

toff = time_off

× T – tskew1

—

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