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PCIMX515CJM6C Datasheet(PDF) 121 Page - Freescale Semiconductor, Inc |
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PCIMX515CJM6C Datasheet(HTML) 121 Page - Freescale Semiconductor, Inc |
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121 / 184 page  Electrical Characteristics i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 121 Preliminary—Subject to Change Without Notice NOTE • The terms WL and BL used in the timing diagrams and tables refer to Word Length (WL) and Byte Length (BL). • The SSI timing diagrams use generic signal names wherein the names used in the i.MX51 reference manual are channel specific signal names. For example, a channel clock referenced in the IOMUXC chapter as AUD3_TXC appears in the timing diagram as TXC. . Figure 89. SSI Transmitter Internal Clock Timing Diagram 3.7.15.1 SSI Transmitter Timing with Internal Clock AUDMUX port 6 AUD6 External – EIM or DISP2 via IOMUX AUDMUX port 7 SSI 3 Internal Table 89. SSI Transmitter Timing with Internal Clock ID Parameter Min Max Unit Internal Clock Operation SS1 (Tx/Rx) CK clock period 81.4 — ns SS2 (Tx/Rx) CK clock high period 36.0 — ns SS3 (Tx/Rx) CK clock rise time — 6.0 ns Table 88. AUDMUX Port Allocation (continued) Port Signal Nomenclature Type and Access SS19 SS1 SS2 SS4 SS3 SS5 SS6 SS8 SS10 SS12 SS14 SS18 SS15 SS17 SS16 SS43 SS42 Note: SRXD input in synchronous mode only TXC (Output) TXFS (wl) (Output) TXFS (bl) (Output) RXD (Input) TXD (Output) |
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