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TUSB1310 Datasheet(PDF) 8 Page - Texas Instruments |
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TUSB1310 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 36 page ![]() TUSB1310 SLLSE16C – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com 1.3 Introduction The TUSB1310 is a single port, 5.0-Gbps USB 3.0 physical layer transceiver operating off of a single crystal or an external reference clock. The reference clock frequencies are selectable from 20, 25, 30, and 40 MHz. The TUSB1310 provides a clock to USB link layer controllers. The single reference clock allows the TUSB1310 to provide a cost effective USB 3.0 solution with few external components and a minimum implementation cost. Link controller interfaces to the TUSB1310 are via a PIPE (SuperSpeed) and a ULPI (USB2.0) interface. The 16-bit PIPE operates with a 250-MHz interface clock. The ULPI supports 8-bit operations with a 60-MHz interface clock. USB 3.0 reduces active power and idle power by improving power management. The PIPE interface controls the TUSB1310 low power states which minimizes power consumption. SuperSpeed USB leverages existing USB software infrastructure by keeping the existing software interfaces and software drivers. In addition the SuperSpeed USB retains backward compatibility at the Type-A connector with USB2.0 based PCs and with USB2.0 cables. Figure 1-1. Typical Application 1.4 Functional Block Diagram The USB physical layer handles the low level USB protocol and signaling. This includes data serialization and deserialization, 8b/10b encoding, analog buffers, elastic buffers and receiver detection. It shifts the clock domain of the data from the USB rate to one that is compatible with the link layer controller. The SuperSpeed USB contains SSTXP/SSTXN and SSRXP/SSRXP differential pairs and uses the PIPE to communicate with the link layer controller. The Non-SuperSpeed USB has a DP/DM differential pair and communicates with the link layer controller via the ULPI. The TUSB1310 reference clock is connected to an internal crystal oscillator, spread spectrum clock and PLL which provides clocks to all blocks and to the CLKOUT pin for the link layer controller. A JTAG interface is used for IEEE1149.1 and IEEE1149.6 boundary scan. 8 PRODUCT OVERVIEW Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB1310 |
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