TUSB1310

SLLSE16C – DECEMBER 2009 – REVISED AUGUST 2010

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3. Elastic buffer underflow (can not occur in nominal empty buffer model)

4. Disparity error

3.4.1

Clock Tolerance Compensation

The receiver contains an elastic buffer used to compensate for differences in frequencies between bit

rates at the two ends of a link. The elastic buffer must be capable of holding enough symbols to handle

worst case differences in frequency and worst case intervals between SKP ordered sets. A SKP order set

is a set of symbols transmitted as a group. The SKP ordered sets allows the receiver to adjust the data

stream being received to prevent the elastic buffer from either overflowing or under-flowing due to any

clock tolerance differences.

The TUSB1310 supports two models, nominal half full buffer model and nominal empty buffer mode. For

the nominal half full buffer model, the TUSB1310 monitors the receive data stream. When a Skip ordered

set is received, the TUSB1310 adds or removes one SKP order set from each SKP to manage its elastic

buffer to keep the buffer as close to half full as possible. Only full SKP ordered sets are added or

removed. When a SKP order set is added, the TUSB1310 asserts an “Add SKP” code (001b) on the

RX_STATUS for one clock cycle. When a SKP order set is removed, the RX_STATUS is has a “Remove

SHP” code (010b).

For the nominal empty buffer model the TUSB1310 attempts to keep the elasticity buffer as close to empty

as possible. When no SKP ordered sets have been received, the TUSB1310 will be required to insert SKP

ordered sets into the received data stream.

Table 3-4. RX_STATUS - SKP

RX_STATUS2-0

SKP ADDITION or REMOVAL

LENGTH

001b

1 SKP ordered set added

One clock cycle

010b

1 SKP ordered set removed

3.4.2

Receiver Detection

TX_DETRX_LPBK starts a receiver detection operation to determine if there is a receiver at the other end

of the link. When the receiver detect sequence completes, the PHY_STATUS is asserted for one clock

and drives the RX_STATUS signals to the appropriate code. Once the TX_DETRX_LPBK signal is

asserted, the link layer controller must leave the signal asserted until the PHY_STATUS pulse. When

receiver detection is performed in P3, the PHY_STATUS shows the appropriate receiver detect value until

the TX_DETRX_LPBK is de-asserted.

Table 3-5. RX_STATUS - Receiver Detection

RX_STATUS2-0

DETECTED CONDITION

LENGTH

000b

Receiver not present

One clock cycle

011b

Receiver present

3.4.3

8b/10b Decode Errors

When the TUSB1310 detects an 8b/10b decode error, it will assert an EDB (0xFE) symbol in the data on

the RX_DATA where the bad byte occurred. In the same clock cycle that the EDB symbol is asserted on

the RX_DATA, the 8b/10b decode error code (100b) will be asserted on the RX_STATUS. 8b/10b

decoding error has priority over all other receiver error codes and could mask out a disparity error

occurring on the other byte of data being clocked onto the RX_DATA with the EDB symbol.

20

FUNCTIONAL DESCRIPTION

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