TUSB1310

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SLLSE16C – DECEMBER 2009 – REVISED AUGUST 2010

Load capacitance (Cload) of the crystal varying with the crystal vendors is the total capacitance value of

the entire oscillation circuit system as seen from the crystal. It includes two external capacitors CL1 and

CL2 in Figure 5-4. CVSS below is optional, but recommended for minimum jitter implementation. The

trace length between the decoupling capacitors and the corresponding power pins on the TUSB1310

needs to be minimized. It is also recommended that the trace length from the capacitor pad to the power

or ground plane be minimized.

Figure 5-4. Typical Crystal Connections

5.2

Clock Source Requirements

5.2.1

Clock Source Selection Guide

Reference clock jitter is an important parameter. Jitter on the reference clock will degrade both the

transmit eye and receiver jitter tolerance no matter how clean the rest of the PLL is, thereby impairing

sys-tem performance. Additionally, a particularly jittery reference clock may interfere with PLL lock

detection mechanism, forcing the lock detector to issue an unlock signal. A good quality, low jitter

reference clock is required to achieve compliance with supported USB3.0 standards. For example,

USB3.0 specification requires the random jitter (RJ) component of either RX or TX to be 2.42 ps (random

phase jitter calculated after applying jitter transfer function - JTF). As the PLL typically has a number of

additional jitter components, the reference clock jitter must be considerably below the overall jitter budget.

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DESIGN GUIDELINES

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Product Folder Link(s): TUSB1310