TUSB1310 datasheet(23/36 Pages) TI

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TUSB1310

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SLLSE16C – DECEMBER 2009 – REVISED AUGUST 2010

4.2.2

Function Control (04h-06h)

Address: 04h-06h (Read), 04h(Write), 05h(Set), 06h(Clear)

Table 4-4. Function Control

BITS

NAME

ACCESS

RESET

DESCRIPTION

Selects the required transceiver speed

00b : Enable HS transceiver

01b: Enable FS transceiver

1:00

XcvrSelect

Rd/Wr/S/C

10b: Enable LS transceiver

11b: Enable FS transceiver for LS packets

(FS preamble is automatically pre-pended)

Controls the internal 1.5-k

Ω pullup resister and 45-Ω HS terminations.

Control over bus resistors changes depending on XcvrSelect,

TermSelect

Rd/Wr/S/C

OpMode, DpPulldown and DmPulldown. Since low speed peripherals

never support full speed or hi-speed, providing the 1.5 k

Ω on DM for

low speed is optional.

Selects the required bit encoding style during transmit

00 : Normal operation

01: Non-driving

4:03

OpMode

Rd/Wr/S/C

10: Disable bit-stuff and NRZI encoding

11: Do not automatically add SYNC and EOP when transmitting. Must

be used only for HS packets.

Active High transceiver reset. After the Link sets this bit, the

TUSB1310 must assert the ULPI_DIR and reset the ULPI. When the

reset is completed, the PHY de-asserts the ULPI_DIR and

automatically clears this bit. After de-asserting the ULPI_DIR, the PHY

Reset

Rd/Wr/S/C

must re-assert the ULPI_DIR and send an RX CMD update on the link

layer controller. The link layer controller must wait for the ULPI_DIR to

de-assert before using the ULPI bus. Does not reset the ULPI or ULPI

Active low PHY suspend. Put the TUSB1310 into low power mode.

The PHY can power down all blocks except the full speed receiver,

OTG comparators, and the ULPI pins. The PHY must automatically set

SuspendM

Rd/Wr/S/C

this bit to '1' when low power mode is exited.

0: Low power mode

1: Powered

Reserved

REGISTERS

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