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TX _ CLK

TX _ DATA 15 - 0

TX _ DATAK

1 - 0

Valid Data

Thd 2

Tcyc 2

Tsu 2

PCLK

RX _ DATA

15 - 0

RX _ DATAK

1 - 0

RX _ VALID

RX _STATUS

2 - 0

PHY _ STATUS

Valid Data

Tcyc 3

Tdly 3

TUSB1310

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SLLSE16C – DECEMBER 2009 – REVISED AUGUST 2010

Table 6-1. Power Up and Reset Timing

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNIT

Tcfgin1

Hardware configuration latch-in time from RESETN

Tcfgin2

Time from RESETN to dDriver outputs on strapping pins

RESETN pulse width

µs

RESETN to PHY_STATUS de-assertion

300

µs

6.5.2

PIPE Transmit

Figure 6-2. PIPE Transmit Timing

Table 6-2. PIPE Transmit Timing

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNIT

Tcyc2

TX_CLK Period

Tdty2

TX_CLK Period

Tsu2

Data Setup to TX_CLK rise and TX_CLK fall(1)

Thd2

Data Hold to TX_CLK rise and TX_CLK fall(1)

(1)

This includes TX_DATA15-0, TX_DATAK1-0, TX_ONESZEROS, RATE, TX_DEEMPTH, TX_DETRX_LPBK, TX_ELECIDLE,

TX_MARGIN, TX_SWING, RX_POLARITY, POWER_DOWN1-0.

6.5.3

PIPE Receive

Figure 6-3. PIPE Receive Timing

Table 6-3. PIPE Receive Timing

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNIT

Tcyc3

PCLK Period

Tdty3

PCLK Duty Cycle

PCLK rise and fall to RX_DATA15-0, RX_DATAK1-0, RX_VALID,

Tdly3

RX_STATUS2-0, PHY_STATUS Delay(1)(2)

(1)

Output Load max = 10 pF, min = 5 pF

(2)

Timing is relative to the 50% transition point, not VIH/VIL.

ELECTRICAL SPECIFICATIONS

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