ADE7156_15 datasheet(33/152 Pages) AD

No. de pieza	ADE7156

Descripción Electrónicos	Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver

PDF	152 Pages

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Fabricante Electrónico	AD [Analog Devices]

Página de inicio	http://www.analog.com

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Rev. B | Page 33 of

152

POWER SUPPLY MANAGEMENT (PSM) INTERRUPT

The power supply monitor interrupt alerts the 8052 core of

power supply events. The PSM interrupt is disabled by default.

Setting the EPSM bit in the interrupt enable and Priority 2 SFR

(IEIP2, Address 0xA9) enables the PSM interrupt (see Table 80).

The power management interrupt enable SFR (IPSME,

Address 0xEC) controls the events that result in a PSM

interrupt (see Table 21). Figure 33 illustrates how the PSM

interrupt vector is shared among the PSM interrupt sources.

The PSM interrupt flags are latched and must be cleared by

writing to the IPSMF power management interrupt flag SFR,

Address 0xF8 (see Table 18).

EPSR

FPSR

ESAG

FSAG

EVADC

FVADC

EBAT

FBAT

EBSO

FBSO

EVDCIN

FVDCIN

FPSM

EPSM

TRUE?

PENDING PSM

INTERRUPT

EPSR

RESERVED

ESAG

RESERVED

EVADC*

EBAT*

EBSO

EVDCIN*

FPSR

FPSM

FSAG

RESERVED

FVADC*

FBAT*

FBSO

FVDCIN*

RESERVED

PTI

RESERVED

PSI

EADE

ETI

EPSM

ESI

IPSME ADDR. 0xEC

IPSMF ADDR. 0xF8

IEIP2 ADDR. 0xA9

NOT INVOLVED IN PSM INTERRUPT SIGNAL CHAIN.

*NOT AVAILABLE IN THE ADE7116.

Figure 33. Power Supply Management Interrupt Sources

ADE7156 Datasheet(PDF) 33 Page - Analog Devices

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