ADE7156_15 datasheet(34/152 Pages) AD

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Rev. B | Page 34 of

152

Battery Switchover and Power Supply Restored

PSM Interrupt

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/

ADE7569 can be configured to generate a PSM interrupt when

the source of VSWOUT changes from VDD to VBAT, indicating

battery switchover. Setting the EBSO bit in the power manage-

ment interrupt enable SFR (IPSME, Address 0xEC) enables this

event to generate a PSM interrupt (see Table 21).

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/

ADE7569 can also be configured to generate an interrupt when

the source of VSWOUT changes from VBAT to VDD, indicating that

the VDD power supply has been restored. Setting the EPSR bit in

the power management interrupt enable SFR (IPSME, Address

0xEC) enables this event to generate a PSM interrupt.

The flags in the IPSMF SFR for these interrupts, FBSO and

FPSR, are set regardless of whether the respective enable bits

have been set. The battery switchover and power supply restore

event flags, FBSO and FPSR, are latched. These events must be

cleared by writing a 0 to these bits. Bit 6 (VSWSOURCE) in the

peripheral configuration SFR (PERIPH, Address 0xF4) tracks

the source of VSWOUT. The bit is set when VSWOUT is connected to

VDD and cleared when VSWOUT is connected to VBAT.

VDCIN ADC PSM Interrupt

The ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 can be

configured to generate a PSM interrupt when VDCIN changes

magnitude by more than a configurable threshold. This threshold

is set in the temperature and supply delta SFR (DIFFPROG,

Address 0xF3), which is described in Table 50. See the External

Voltage Measurement section for more information. Setting the

EVADC bit in the power management interrupt enable SFR

(IPSME, Address 0xEC) enables this event to generate a PSM

interrupt. Note that this feature is not available in the ADE7116.

The VDCIN voltage is measured using a dedicated ADC. These

measurements take place in the background at intervals to check

the change in VDCIN. Conversions can also be initiated by writing to

the start ADC measurement SFR (ADCGO, Address 0xD8), as

described in Table 51. The FVADC flag in the power manage-

ment interrupt flag SFR (IPSMF, Address 0xF8) indicates when

a VDCIN measurement is ready. See the External Voltage

Measurement section for details on how VDCIN is measured.

VBAT Monitor PSM Interrupt

The VBAT voltage is measured using a dedicated ADC. These

measurements take place in the background at intervals to

check the change in VBAT. The FBAT bit is set when the battery

level is lower than the threshold set in the battery detection

threshold SFR (BATVTH, Address 0xFA), described in Table 52,

or when a new measurement is ready in the battery ADC value

SFR (BATADC, Address 0xDF), described in Table 54. See the

Battery Measurement section for more information. Setting the

EBAT bit in the power management interrupt enable SFR

(IPSME, Address 0xEC) enables this event to generate a PSM

interrupt. Note that this feature is not available in the ADE7116.

VDCIN Monitor PSM Interrupt

The VDCIN voltage is monitored by a comparator. The FVDCIN

bit in the power management interrupt flag SFR (IPSMF,

Address 0xF8) is set when the VDCIN input level is lower than

1.2 V. Setting the EVDCIN bit in the IPSME SFR enables this

event to generate a PSM interrupt. This event, which is associated

with the SAG monitoring, can be used to detect that a power

supply (VDD) is compromised and to trigger further actions

prior to initiating a switch from VDD to VBAT. Note that this

feature is not available in the ADE7116.

SAG Monitor PSM Interrupt

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/

ADE7569 energy measurement DSP monitors the ac voltage

input at the VP and VN input pins. The SAGLVL register

(Address 0x14) is used to set the threshold for a line voltage

SAG event. The FSAG bit in the power management interrupt

flag SFR (IPSMF, Address 0xF8) is set if the line voltage stays

below the level set in the SAGLVL register for the number of

line cycles set in the SAGCYC register (Address 0x13). See the

Line Voltage SAG Detection section for more information.

Setting the ESAG bit in the power management interrupt enable

SFR (IPSME, Address 0xEC) enables this event to generate a

PSM interrupt.

ADE7156 Datasheet(PDF) 34 Page - Analog Devices

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