ADE7156_15 datasheet(78/152 Pages) AD

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

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Table 50. Temperature and Supply Delta SFR (DIFFPROG, Address 0xF3)

Bit

Mnemonic

Default

Description

[7:6]

Reserved

Reserved.

[5:3]

TEMP_DIFF

Difference threshold between last temperature measurement interrupting 8052 and new

temperature measurement that should interrupt 8052.

TEMP_DIFF

Result

000

No interrupt

001

1 LSB (≈ 0.8°C)

010

2 LSB (≈ 1.6°C)

011

3 LSB (≈ 2.4°C)

100

4 LSB (≈ 3.2°C)

101

5 LSB (≈ 4°C)

110

6 LSB (≈ 4.8°C)

111

Every temperature measurement

[2:0]

VDCIN_DIFF

Difference threshold between last external voltage measurement interrupting 8052 and new

external measurement that should interrupt 8052.

VDCIN_DIFF

Result

000

No interrupt

001

1 LSB (≈ 120 mV)

010

2 LSB (≈ 240 mV)

011

3 LSB (≈ 360 mV)

100

4 LSB (≈ 480 mV)

101

5 LSB (≈ 600 mV)

110

6 LSB (≈ 720 mV)

111

Every VDCIN measurement

Table 51. Start ADC Measurement SFR (ADCGO, Address 0xD8)

Bit

Address

Mnemonic

Default

Description

0xDF

PLLACK

Set this bit to clear the PLL fault bit, PLL_FLT, in the PERIPH register (Address

0xF4). A PLL fault is generated if a reset is caused because the PLL lost lock.

[6:3]

0xDE to 0xDB

Reserved

Reserved.

0xDA

VDCIN_ADC_GO

Set this bit to initiate an external voltage measurement. This bit is cleared

when the measurement request is received by the ADC.

0xD9

TEMP_ADC_GO

Set this bit to initiate a temperature measurement. This bit is cleared when

the measurement request is received by the ADC.

0xD8

BATT_ADC_GO

Set this bit to initiate a battery measurement. This bit is cleared when the

measurement request is received by the ADC.

Table 52. Battery Detection Threshold SFR (BATVTH, Address 0xFA)

Bit

Mnemonic

Default

Description

[7:0]

BATVTH

The battery ADC value is compared to this register, the battery threshold register. If

BATADC is lower than the threshold, an interrupt is generated.

Table 53. VDCIN ADC Value SFR (VDCINADC, Address 0xEF)

Bit

Mnemonic

Default

Description

[7:0]

VDCINADC

The VDCINADC value in this register is updated when an ADC interrupt occurs.

Table 54. Battery ADC Value SFR (BATADC, Address 0xDF)

Bit

Mnemonic

Default

Description

[7:0]

BATADC

The battery ADC value in this register is updated when an ADC interrupt occurs.

Table 55. Temperature ADC Value SFR (TEMPADC, Address 0xD7)

Bit

Mnemonic

Default

Description

[7:0]

TEMPADC

The temperature ADC value in this register is updated when an ADC interrupt occurs.

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