ADE7156_15 datasheet(100/152 Pages) AD

100 / 152 page

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Rev. B | Page 100 of 1

LCD DRIVER

Using shared pins, the LCD module is capable of directly driving

an LCD panel of 17 × 4 segments without compromising any

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

functions. It is capable of driving LCDs with 2×, 3×, and 4× multi-

plexing. The LCD waveform voltages generated through internal

charge pump circuitry support up to 5 V LCDs for the ADE7156/

ADE7166/ADE7169/ADE7566/ADE7569. An external resistor

ladder for LCD waveform voltage generation is also supported.

Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/

ADE7569 has an embedded LCD control circuit, driver, and

power supply circuit. The LCD module is functional in all

operating modes (see the Operating Modes section).

LCD REGISTERS

There are six LCD control registers that configure the driver for

the specific type of LCD in the end system and set up the user

display preferences. The LCD configuration SFR (LCDCON,

Address 0x95), LCD Configuration X SFR (LCDCONX,

Address 0x9C), and LCD Configuration Y SFR (LCDCONY,

Address 0xB1) contain general LCD driver configuration

information including the LCD enable and reset, as well as the

method of LCD voltage generation and multiplex level. The

LCD clock SFR (LCDCLK, Address 0x96) configures timing

settings for LCD frame rate and blink rate. LCD pins are

configured for LCD functionality in the LCD segment enable

SFR (LCDSEGE, Address 0x97) and the LCD Segment Enable 2

SFR (LCDSEGE2, Address 0xED).

Table 87. LCD Driver SFRs

SFR Address

R/W

Mnemonic

Description

0x95

R/W

LCDCON

LCD configuration SFR (see Table 88).

0x96

R/W

LCDCLK

LCD clock (see

Table 92).

0x97

R/W

LCDSEGE

LCD segment Enable (see Table 95).

0x9C

R/W

LCDCONX

LCD configuration X (see Table 89).

0xAC

R/W

LCDPTR

LCD pointer (see Table 96).

0xAE

R/W

LCDDAT

LCD data (see Table 97).

0xB1

R/W

LCDCONY

LCD configuration Y (see Table 91).

0xED

R/W

LCDSEGE2

LCD segment Enable 2 (see Table 98).

Table 88. LCD Configuration SFR (LCDCON, Address 0x95)

Bit

Mnemonic

Default

Description

LCDEN

LCD enable. If this bit is set, the LCD driver is enabled.

LCDRST

LCD data registers reset. If this bit is set, the LCD data registers are reset to 0.

BLINKEN

Blink mode enable bit. If this bit is set, blink mode is enabled. The blink mode is configured by the

BLKMOD and BLKFREQ bits in the LCD clock SFR (LCDCLK, Address 0x96).

LCDPSM2

Forces LCD off when in PSM2 (sleep) mode. Note that the internal voltage reference must be enabled by

setting the REF_BAT_EN bit in the Peripheral Configuration SFR (PERIPH, Address 0xF4) to allow LCD

operation in PSM2 mode.

LCDPSM2

Result

The LCD is disabled or enabled in PSM2 by the LCDEN bit

The LCD is disabled in PSM2 regardless of LCDEN setting

CLKSEL

LCD clock selection.

CLKSEL

Result

fLCDCLK = 2048 Hz

fLCDCLK = 128 Hz

BIAS

Bias mode.

BIAS

Result

1/2

1/3

[1:0]

LMUX

LCD multiplex level.

LMUX

Result

Reserved.

2× multiplexing. FP27/COM3 is used as FP27, and FP28/COM2 is used as FP28.

3× multiplexing. FP27/COM3 is used as FP27, and FP28/COM2 is used as COM2.

4× multiplexing. FP27/COM3 is used as COM3, and FP28/COM2 is used as COM2.

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