8T73S208A-01 datasheet(3/22 Pages) IDT

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REVISION 1 06/15/15

2.5V, 3.3V DIFFERENTIAL LVPECL CLOCK DIVIDER AND BUFFER

8T73S208A-01 DATA SHEET

Function Tables

Input Frequency Divider Operation

The FSEL1 and FSEL0 control pins configure the input frequency

divider. In the default state (FSEL[1:0] are set to logic 0:0 or left open)

the output frequency is equal to the input frequency (divide-by-1).

The other FSEL[1:0] settings configure the input divider to

divide-by-2, 4 or 8, respectively.

NOTE: FSEL1, FSEL0 are asynchronous controls

Output Enable Operation

The output enable/disable state of each individual differential output

Qx, nQx can be set by the content of the I2C register (see Table 3C).

A logic zero to an I2C bit in register 0 enables the corresponding

differential output, while a logic one disables the differential output

(see Table 3B). After each power cycle, the device resets all I2C bits

(Dn) to its default state (logic 1) and all Qx, nQx outputs are disabled.

After the first valid I2C write, the output enable state is controlled by

the I2C register. Setting and changing the output enable state through

the I2C interface is asynchronous to the input reference clock.

I2C Interface Protocol

The 8T73S208A-01 uses an I2C slave interface for writing and

reading the device configuration to and from the on-chip

configuration registers. This device uses the standard I2C write

format for a write transaction, and a standard I2C read format for a

read transaction. Figure 1 defines the I2C elements of the standard

I2C transaction. These elements consist of a start bit, data bytes, an

acknowledge or Not-Acknowledge bit and the stop bit. These

elements are arranged to make up the complete I2C transactions as

shown in Figure 2 and Figure 3. Figure 2 is a write transaction while

Figure 3 is read transaction. The 7-bit I2C slave address of the

8T73S208A-01 is a combination of a 5-bit fixed addresses and two

variable bits which are set by the hardware pins ADR[1:0] (binary

11010, ADR1, ADR0). Bit 0 of slave address is used by the bus

controller to select either the read or write mode. The hardware pins

ADR1 and ADR0 and should be individually set by the user to avoid

address conflicts of multiple 8T73S208A-01 devices on the same

bus.

START (S) – defined as high-to-low transition on SDA while holding

SCL HIGH.

DATA – between START and STOP cycles, SDA is synchronous with

SCL. Data may change only when SCL is LOW and must be stable

when SCL is HIGH.

ACKNOWLEDGE (A) – SDA is driven LOW before the SCL rising

edge and held LOW until the SCL falling edge.

STOP (S) – defined as low-to-high transition on SDA while holding

SCL HIGH

S –

Start or Repeated Start

W –

R/W is set for Write

R –

R/W is set for Read

A –Ack

DevAdd –

7 bit Device Address

P –

Stop

Table 3A. FSEL[1:0] Input Selection Function Table

Input

Operation

FSEL1

FSEL0

0 (default)

fQ[7:0] = fREF ÷ 1

fQ[7:0] = fREF ÷ 2

fQ[7:0] = fREF ÷ 4

fQ[7:0] = fREF ÷ 8

Table 3B. Individual Output Enable Control

Bit

Operation

Output Qx, nQx is enabled.

1 (default)

Output Qx, nQx is disabled in high-impedance

state.

Table 3C. Individual output enable control

Bit

D6D5D4D3

D2D1D0

Output

Default

1111

111

Table 3D. I2C Slave Address

ADR1

ADR0

R/W

SCL

SDA

START

Valid Data

Acknowledge

STOP

Figure 1: Standard I2C Transaction

SW A

A P

DevAdd

Data Byte

SR A

A P

DevAdd

Data Byte

Figure 2: Write Transaction

Figure 3: Read Transaction

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